Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
11 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
14 #include <dt-bindings/interconnect/qcom,sdm845.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/phy/phy-qcom-qusb2.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
19 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
22 #include <dt-bindings/thermal/thermal.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
73 reserved-memory {
74 #address-cells = <2>;
75 #size-cells = <2>;
80 no-map;
85 no-map;
90 no-map;
94 compatible = "qcom,cmd-db";
96 no-map;
101 no-map;
106 no-map;
110 compatible = "qcom,rmtfs-mem";
112 no-map;
114 qcom,client-id = <1>;
120 no-map;
125 no-map;
130 no-map;
135 no-map;
140 no-map;
145 no-map;
150 no-map;
155 no-map;
160 no-map;
165 no-map;
170 no-map;
175 no-map;
180 no-map;
185 #address-cells = <2>;
186 #size-cells = <0>;
192 enable-method = "psci";
193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
196 capacity-dmips-mhz = <607>;
197 dynamic-power-coefficient = <100>;
198 qcom,freq-domain = <&cpufreq_hw 0>;
199 #cooling-cells = <2>;
200 next-level-cache = <&L2_0>;
201 L2_0: l2-cache {
203 next-level-cache = <&L3_0>;
204 L3_0: l3-cache {
214 enable-method = "psci";
215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
218 capacity-dmips-mhz = <607>;
219 dynamic-power-coefficient = <100>;
220 qcom,freq-domain = <&cpufreq_hw 0>;
221 #cooling-cells = <2>;
222 next-level-cache = <&L2_100>;
223 L2_100: l2-cache {
225 next-level-cache = <&L3_0>;
233 enable-method = "psci";
234 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
237 capacity-dmips-mhz = <607>;
238 dynamic-power-coefficient = <100>;
239 qcom,freq-domain = <&cpufreq_hw 0>;
240 #cooling-cells = <2>;
241 next-level-cache = <&L2_200>;
242 L2_200: l2-cache {
244 next-level-cache = <&L3_0>;
252 enable-method = "psci";
253 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
256 capacity-dmips-mhz = <607>;
257 dynamic-power-coefficient = <100>;
258 qcom,freq-domain = <&cpufreq_hw 0>;
259 #cooling-cells = <2>;
260 next-level-cache = <&L2_300>;
261 L2_300: l2-cache {
263 next-level-cache = <&L3_0>;
271 enable-method = "psci";
272 capacity-dmips-mhz = <1024>;
273 cpu-idle-states = <&BIG_CPU_SLEEP_0
276 dynamic-power-coefficient = <396>;
277 qcom,freq-domain = <&cpufreq_hw 1>;
278 #cooling-cells = <2>;
279 next-level-cache = <&L2_400>;
280 L2_400: l2-cache {
282 next-level-cache = <&L3_0>;
290 enable-method = "psci";
291 capacity-dmips-mhz = <1024>;
292 cpu-idle-states = <&BIG_CPU_SLEEP_0
295 dynamic-power-coefficient = <396>;
296 qcom,freq-domain = <&cpufreq_hw 1>;
297 #cooling-cells = <2>;
298 next-level-cache = <&L2_500>;
299 L2_500: l2-cache {
301 next-level-cache = <&L3_0>;
309 enable-method = "psci";
310 capacity-dmips-mhz = <1024>;
311 cpu-idle-states = <&BIG_CPU_SLEEP_0
314 dynamic-power-coefficient = <396>;
315 qcom,freq-domain = <&cpufreq_hw 1>;
316 #cooling-cells = <2>;
317 next-level-cache = <&L2_600>;
318 L2_600: l2-cache {
320 next-level-cache = <&L3_0>;
328 enable-method = "psci";
329 capacity-dmips-mhz = <1024>;
330 cpu-idle-states = <&BIG_CPU_SLEEP_0
333 dynamic-power-coefficient = <396>;
334 qcom,freq-domain = <&cpufreq_hw 1>;
335 #cooling-cells = <2>;
336 next-level-cache = <&L2_700>;
337 L2_700: l2-cache {
339 next-level-cache = <&L3_0>;
343 cpu-map {
379 idle-states {
380 entry-method = "psci";
382 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
383 compatible = "arm,idle-state";
384 idle-state-name = "little-power-down";
385 arm,psci-suspend-param = <0x40000003>;
386 entry-latency-us = <350>;
387 exit-latency-us = <461>;
388 min-residency-us = <1890>;
389 local-timer-stop;
392 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
393 compatible = "arm,idle-state";
394 idle-state-name = "little-rail-power-down";
395 arm,psci-suspend-param = <0x40000004>;
396 entry-latency-us = <360>;
397 exit-latency-us = <531>;
398 min-residency-us = <3934>;
399 local-timer-stop;
402 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
403 compatible = "arm,idle-state";
404 idle-state-name = "big-power-down";
405 arm,psci-suspend-param = <0x40000003>;
406 entry-latency-us = <264>;
407 exit-latency-us = <621>;
408 min-residency-us = <952>;
409 local-timer-stop;
412 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
413 compatible = "arm,idle-state";
414 idle-state-name = "big-rail-power-down";
415 arm,psci-suspend-param = <0x40000004>;
416 entry-latency-us = <702>;
417 exit-latency-us = <1061>;
418 min-residency-us = <4488>;
419 local-timer-stop;
422 CLUSTER_SLEEP_0: cluster-sleep-0 {
423 compatible = "arm,idle-state";
424 idle-state-name = "cluster-power-down";
425 arm,psci-suspend-param = <0x400000F4>;
426 entry-latency-us = <3263>;
427 exit-latency-us = <6562>;
428 min-residency-us = <9987>;
429 local-timer-stop;
435 compatible = "arm,armv8-pmuv3";
440 compatible = "arm,armv8-timer";
448 xo_board: xo-board {
449 compatible = "fixed-clock";
450 #clock-cells = <0>;
451 clock-frequency = <38400000>;
452 clock-output-names = "xo_board";
455 sleep_clk: sleep-clk {
456 compatible = "fixed-clock";
457 #clock-cells = <0>;
458 clock-frequency = <32764>;
464 compatible = "qcom,scm-sdm845", "qcom,scm";
468 adsp_pas: remoteproc-adsp {
469 compatible = "qcom,sdm845-adsp-pas";
471 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
476 interrupt-names = "wdog", "fatal", "ready",
477 "handover", "stop-ack";
480 clock-names = "xo";
482 memory-region = <&adsp_mem>;
484 qcom,smem-states = <&adsp_smp2p_out 0>;
485 qcom,smem-state-names = "stop";
489 glink-edge {
492 qcom,remote-pid = <2>;
496 qcom,glink-channels = "fastrpcglink-apps-dsp";
498 #address-cells = <1>;
499 #size-cells = <0>;
501 compute-cb@3 {
502 compatible = "qcom,fastrpc-compute-cb";
507 compute-cb@4 {
508 compatible = "qcom,fastrpc-compute-cb";
516 cdsp_pas: remoteproc-cdsp {
517 compatible = "qcom,sdm845-cdsp-pas";
519 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
524 interrupt-names = "wdog", "fatal", "ready",
525 "handover", "stop-ack";
528 clock-names = "xo";
530 memory-region = <&cdsp_mem>;
532 qcom,smem-states = <&cdsp_smp2p_out 0>;
533 qcom,smem-state-names = "stop";
537 glink-edge {
540 qcom,remote-pid = <5>;
544 qcom,glink-channels = "fastrpcglink-apps-dsp";
546 #address-cells = <1>;
547 #size-cells = <0>;
549 compute-cb@1 {
550 compatible = "qcom,fastrpc-compute-cb";
555 compute-cb@2 {
556 compatible = "qcom,fastrpc-compute-cb";
561 compute-cb@3 {
562 compatible = "qcom,fastrpc-compute-cb";
567 compute-cb@4 {
568 compatible = "qcom,fastrpc-compute-cb";
573 compute-cb@5 {
574 compatible = "qcom,fastrpc-compute-cb";
579 compute-cb@6 {
580 compatible = "qcom,fastrpc-compute-cb";
585 compute-cb@7 {
586 compatible = "qcom,fastrpc-compute-cb";
591 compute-cb@8 {
592 compatible = "qcom,fastrpc-compute-cb";
601 compatible = "qcom,tcsr-mutex";
603 #hwlock-cells = <1>;
608 memory-region = <&smem_mem>;
612 smp2p-cdsp {
620 qcom,local-pid = <0>;
621 qcom,remote-pid = <5>;
623 cdsp_smp2p_out: master-kernel {
624 qcom,entry-name = "master-kernel";
625 #qcom,smem-state-cells = <1>;
628 cdsp_smp2p_in: slave-kernel {
629 qcom,entry-name = "slave-kernel";
631 interrupt-controller;
632 #interrupt-cells = <2>;
636 smp2p-lpass {
644 qcom,local-pid = <0>;
645 qcom,remote-pid = <2>;
647 adsp_smp2p_out: master-kernel {
648 qcom,entry-name = "master-kernel";
649 #qcom,smem-state-cells = <1>;
652 adsp_smp2p_in: slave-kernel {
653 qcom,entry-name = "slave-kernel";
655 interrupt-controller;
656 #interrupt-cells = <2>;
660 smp2p-mpss {
665 qcom,local-pid = <0>;
666 qcom,remote-pid = <1>;
668 modem_smp2p_out: master-kernel {
669 qcom,entry-name = "master-kernel";
670 #qcom,smem-state-cells = <1>;
673 modem_smp2p_in: slave-kernel {
674 qcom,entry-name = "slave-kernel";
675 interrupt-controller;
676 #interrupt-cells = <2>;
680 smp2p-slpi {
685 qcom,local-pid = <0>;
686 qcom,remote-pid = <3>;
688 slpi_smp2p_out: master-kernel {
689 qcom,entry-name = "master-kernel";
690 #qcom,smem-state-cells = <1>;
693 slpi_smp2p_in: slave-kernel {
694 qcom,entry-name = "slave-kernel";
695 interrupt-controller;
696 #interrupt-cells = <2>;
700 psci {
701 compatible = "arm,psci-1.0";
706 #address-cells = <2>;
707 #size-cells = <2>;
709 dma-ranges = <0 0 0 0 0x10 0>;
710 compatible = "simple-bus";
712 gcc: clock-controller@100000 {
713 compatible = "qcom,gcc-sdm845";
715 #clock-cells = <1>;
716 #reset-cells = <1>;
717 #power-domain-cells = <1>;
723 #address-cells = <1>;
724 #size-cells = <1>;
726 qusb2p_hstx_trim: hstx-trim-primary@1eb {
731 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
738 compatible = "qcom,prng-ee";
741 clock-names = "core";
745 compatible = "qcom,geni-se-qup";
747 clock-names = "m-ahb", "s-ahb";
750 #address-cells = <2>;
751 #size-cells = <2>;
756 compatible = "qcom,geni-i2c";
758 clock-names = "se";
760 pinctrl-names = "default";
761 pinctrl-0 = <&qup_i2c0_default>;
763 #address-cells = <1>;
764 #size-cells = <0>;
769 compatible = "qcom,geni-spi";
771 clock-names = "se";
773 pinctrl-names = "default";
774 pinctrl-0 = <&qup_spi0_default>;
776 #address-cells = <1>;
777 #size-cells = <0>;
782 compatible = "qcom,geni-uart";
784 clock-names = "se";
786 pinctrl-names = "default";
787 pinctrl-0 = <&qup_uart0_default>;
793 compatible = "qcom,geni-i2c";
795 clock-names = "se";
797 pinctrl-names = "default";
798 pinctrl-0 = <&qup_i2c1_default>;
800 #address-cells = <1>;
801 #size-cells = <0>;
806 compatible = "qcom,geni-spi";
808 clock-names = "se";
810 pinctrl-names = "default";
811 pinctrl-0 = <&qup_spi1_default>;
813 #address-cells = <1>;
814 #size-cells = <0>;
819 compatible = "qcom,geni-uart";
821 clock-names = "se";
823 pinctrl-names = "default";
824 pinctrl-0 = <&qup_uart1_default>;
830 compatible = "qcom,geni-i2c";
832 clock-names = "se";
834 pinctrl-names = "default";
835 pinctrl-0 = <&qup_i2c2_default>;
837 #address-cells = <1>;
838 #size-cells = <0>;
843 compatible = "qcom,geni-spi";
845 clock-names = "se";
847 pinctrl-names = "default";
848 pinctrl-0 = <&qup_spi2_default>;
850 #address-cells = <1>;
851 #size-cells = <0>;
856 compatible = "qcom,geni-uart";
858 clock-names = "se";
860 pinctrl-names = "default";
861 pinctrl-0 = <&qup_uart2_default>;
867 compatible = "qcom,geni-i2c";
869 clock-names = "se";
871 pinctrl-names = "default";
872 pinctrl-0 = <&qup_i2c3_default>;
874 #address-cells = <1>;
875 #size-cells = <0>;
880 compatible = "qcom,geni-spi";
882 clock-names = "se";
884 pinctrl-names = "default";
885 pinctrl-0 = <&qup_spi3_default>;
887 #address-cells = <1>;
888 #size-cells = <0>;
893 compatible = "qcom,geni-uart";
895 clock-names = "se";
897 pinctrl-names = "default";
898 pinctrl-0 = <&qup_uart3_default>;
904 compatible = "qcom,geni-i2c";
906 clock-names = "se";
908 pinctrl-names = "default";
909 pinctrl-0 = <&qup_i2c4_default>;
911 #address-cells = <1>;
912 #size-cells = <0>;
917 compatible = "qcom,geni-spi";
919 clock-names = "se";
921 pinctrl-names = "default";
922 pinctrl-0 = <&qup_spi4_default>;
924 #address-cells = <1>;
925 #size-cells = <0>;
930 compatible = "qcom,geni-uart";
932 clock-names = "se";
934 pinctrl-names = "default";
935 pinctrl-0 = <&qup_uart4_default>;
941 compatible = "qcom,geni-i2c";
943 clock-names = "se";
945 pinctrl-names = "default";
946 pinctrl-0 = <&qup_i2c5_default>;
948 #address-cells = <1>;
949 #size-cells = <0>;
954 compatible = "qcom,geni-spi";
956 clock-names = "se";
958 pinctrl-names = "default";
959 pinctrl-0 = <&qup_spi5_default>;
961 #address-cells = <1>;
962 #size-cells = <0>;
967 compatible = "qcom,geni-uart";
969 clock-names = "se";
971 pinctrl-names = "default";
972 pinctrl-0 = <&qup_uart5_default>;
978 compatible = "qcom,geni-i2c";
980 clock-names = "se";
982 pinctrl-names = "default";
983 pinctrl-0 = <&qup_i2c6_default>;
985 #address-cells = <1>;
986 #size-cells = <0>;
991 compatible = "qcom,geni-spi";
993 clock-names = "se";
995 pinctrl-names = "default";
996 pinctrl-0 = <&qup_spi6_default>;
998 #address-cells = <1>;
999 #size-cells = <0>;
1004 compatible = "qcom,geni-uart";
1006 clock-names = "se";
1008 pinctrl-names = "default";
1009 pinctrl-0 = <&qup_uart6_default>;
1015 compatible = "qcom,geni-i2c";
1017 clock-names = "se";
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&qup_i2c7_default>;
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1028 compatible = "qcom,geni-spi";
1030 clock-names = "se";
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&qup_spi7_default>;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1041 compatible = "qcom,geni-uart";
1043 clock-names = "se";
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&qup_uart7_default>;
1053 compatible = "qcom,geni-se-qup";
1055 clock-names = "m-ahb", "s-ahb";
1058 #address-cells = <2>;
1059 #size-cells = <2>;
1064 compatible = "qcom,geni-i2c";
1066 clock-names = "se";
1068 pinctrl-names = "default";
1069 pinctrl-0 = <&qup_i2c8_default>;
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1077 compatible = "qcom,geni-spi";
1079 clock-names = "se";
1081 pinctrl-names = "default";
1082 pinctrl-0 = <&qup_spi8_default>;
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1090 compatible = "qcom,geni-uart";
1092 clock-names = "se";
1094 pinctrl-names = "default";
1095 pinctrl-0 = <&qup_uart8_default>;
1101 compatible = "qcom,geni-i2c";
1103 clock-names = "se";
1105 pinctrl-names = "default";
1106 pinctrl-0 = <&qup_i2c9_default>;
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1114 compatible = "qcom,geni-spi";
1116 clock-names = "se";
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&qup_spi9_default>;
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1127 compatible = "qcom,geni-debug-uart";
1129 clock-names = "se";
1131 pinctrl-names = "default";
1132 pinctrl-0 = <&qup_uart9_default>;
1138 compatible = "qcom,geni-i2c";
1140 clock-names = "se";
1142 pinctrl-names = "default";
1143 pinctrl-0 = <&qup_i2c10_default>;
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1151 compatible = "qcom,geni-spi";
1153 clock-names = "se";
1155 pinctrl-names = "default";
1156 pinctrl-0 = <&qup_spi10_default>;
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1164 compatible = "qcom,geni-uart";
1166 clock-names = "se";
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&qup_uart10_default>;
1175 compatible = "qcom,geni-i2c";
1177 clock-names = "se";
1179 pinctrl-names = "default";
1180 pinctrl-0 = <&qup_i2c11_default>;
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1188 compatible = "qcom,geni-spi";
1190 clock-names = "se";
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&qup_spi11_default>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1201 compatible = "qcom,geni-uart";
1203 clock-names = "se";
1205 pinctrl-names = "default";
1206 pinctrl-0 = <&qup_uart11_default>;
1212 compatible = "qcom,geni-i2c";
1214 clock-names = "se";
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&qup_i2c12_default>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1225 compatible = "qcom,geni-spi";
1227 clock-names = "se";
1229 pinctrl-names = "default";
1230 pinctrl-0 = <&qup_spi12_default>;
1232 #address-cells = <1>;
1233 #size-cells = <0>;
1238 compatible = "qcom,geni-uart";
1240 clock-names = "se";
1242 pinctrl-names = "default";
1243 pinctrl-0 = <&qup_uart12_default>;
1249 compatible = "qcom,geni-i2c";
1251 clock-names = "se";
1253 pinctrl-names = "default";
1254 pinctrl-0 = <&qup_i2c13_default>;
1256 #address-cells = <1>;
1257 #size-cells = <0>;
1262 compatible = "qcom,geni-spi";
1264 clock-names = "se";
1266 pinctrl-names = "default";
1267 pinctrl-0 = <&qup_spi13_default>;
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1275 compatible = "qcom,geni-uart";
1277 clock-names = "se";
1279 pinctrl-names = "default";
1280 pinctrl-0 = <&qup_uart13_default>;
1286 compatible = "qcom,geni-i2c";
1288 clock-names = "se";
1290 pinctrl-names = "default";
1291 pinctrl-0 = <&qup_i2c14_default>;
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1299 compatible = "qcom,geni-spi";
1301 clock-names = "se";
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_spi14_default>;
1306 #address-cells = <1>;
1307 #size-cells = <0>;
1312 compatible = "qcom,geni-uart";
1314 clock-names = "se";
1316 pinctrl-names = "default";
1317 pinctrl-0 = <&qup_uart14_default>;
1323 compatible = "qcom,geni-i2c";
1325 clock-names = "se";
1327 pinctrl-names = "default";
1328 pinctrl-0 = <&qup_i2c15_default>;
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1336 compatible = "qcom,geni-spi";
1338 clock-names = "se";
1340 pinctrl-names = "default";
1341 pinctrl-0 = <&qup_spi15_default>;
1343 #address-cells = <1>;
1344 #size-cells = <0>;
1349 compatible = "qcom,geni-uart";
1351 clock-names = "se";
1353 pinctrl-names = "default";
1354 pinctrl-0 = <&qup_uart15_default>;
1360 cache-controller@1100000 {
1361 compatible = "qcom,sdm845-llcc";
1363 reg-names = "llcc_base", "llcc_broadcast_base";
1368 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
1369 "jedec,ufs-2.0";
1373 phy-names = "ufsphy";
1374 lanes-per-direction = <2>;
1375 power-domains = <&gcc UFS_PHY_GDSC>;
1376 #reset-cells = <1>;
1380 clock-names =
1398 freq-table-hz =
1412 compatible = "qcom,sdm845-qmp-ufs-phy";
1414 #address-cells = <2>;
1415 #size-cells = <2>;
1417 clock-names = "ref",
1423 reset-names = "ufsphy";
1432 #phy-cells = <0>;
1442 compatible = "qcom,sdm845-pinctrl";
1445 gpio-controller;
1446 #gpio-cells = <2>;
1447 interrupt-controller;
1448 #interrupt-cells = <2>;
1449 gpio-ranges = <&tlmm 0 0 150>;
1451 qspi_clk: qspi-clk {
1458 qspi_cs0: qspi-cs0 {
1465 qspi_cs1: qspi-cs1 {
1472 qspi_data01: qspi-data01 {
1473 pinmux-data {
1479 qspi_data12: qspi-data12 {
1480 pinmux-data {
1486 qup_i2c0_default: qup-i2c0-default {
1493 qup_i2c1_default: qup-i2c1-default {
1500 qup_i2c2_default: qup-i2c2-default {
1507 qup_i2c3_default: qup-i2c3-default {
1514 qup_i2c4_default: qup-i2c4-default {
1521 qup_i2c5_default: qup-i2c5-default {
1528 qup_i2c6_default: qup-i2c6-default {
1535 qup_i2c7_default: qup-i2c7-default {
1542 qup_i2c8_default: qup-i2c8-default {
1549 qup_i2c9_default: qup-i2c9-default {
1556 qup_i2c10_default: qup-i2c10-default {
1563 qup_i2c11_default: qup-i2c11-default {
1570 qup_i2c12_default: qup-i2c12-default {
1577 qup_i2c13_default: qup-i2c13-default {
1584 qup_i2c14_default: qup-i2c14-default {
1591 qup_i2c15_default: qup-i2c15-default {
1598 qup_spi0_default: qup-spi0-default {
1606 qup_spi1_default: qup-spi1-default {
1614 qup_spi2_default: qup-spi2-default {
1622 qup_spi3_default: qup-spi3-default {
1630 qup_spi4_default: qup-spi4-default {
1638 qup_spi5_default: qup-spi5-default {
1646 qup_spi6_default: qup-spi6-default {
1654 qup_spi7_default: qup-spi7-default {
1662 qup_spi8_default: qup-spi8-default {
1670 qup_spi9_default: qup-spi9-default {
1678 qup_spi10_default: qup-spi10-default {
1686 qup_spi11_default: qup-spi11-default {
1694 qup_spi12_default: qup-spi12-default {
1702 qup_spi13_default: qup-spi13-default {
1710 qup_spi14_default: qup-spi14-default {
1718 qup_spi15_default: qup-spi15-default {
1726 qup_uart0_default: qup-uart0-default {
1733 qup_uart1_default: qup-uart1-default {
1740 qup_uart2_default: qup-uart2-default {
1747 qup_uart3_default: qup-uart3-default {
1754 qup_uart4_default: qup-uart4-default {
1761 qup_uart5_default: qup-uart5-default {
1768 qup_uart6_default: qup-uart6-default {
1775 qup_uart7_default: qup-uart7-default {
1782 qup_uart8_default: qup-uart8-default {
1789 qup_uart9_default: qup-uart9-default {
1796 qup_uart10_default: qup-uart10-default {
1803 qup_uart11_default: qup-uart11-default {
1810 qup_uart12_default: qup-uart12-default {
1817 qup_uart13_default: qup-uart13-default {
1824 qup_uart14_default: qup-uart14-default {
1831 qup_uart15_default: qup-uart15-default {
1840 compatible = "qcom,sdm845-mss-pil";
1842 reg-names = "qdsp6", "rmb";
1844 interrupts-extended =
1851 interrupt-names = "wdog", "fatal", "ready",
1852 "handover", "stop-ack",
1853 "shutdown-ack";
1863 clock-names = "iface", "bus", "mem", "gpll0_mss",
1866 qcom,smem-states = <&modem_smp2p_out 0>;
1867 qcom,smem-state-names = "stop";
1871 reset-names = "mss_restart", "pdc_reset";
1873 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1875 power-domains = <&aoss_qmp 2>,
1879 power-domain-names = "load_state", "cx", "mx", "mss";
1882 memory-region = <&mba_region>;
1886 memory-region = <&mpss_region>;
1889 glink-edge {
1892 qcom,remote-pid = <1>;
1897 gpucc: clock-controller@5090000 {
1898 compatible = "qcom,sdm845-gpucc";
1900 #clock-cells = <1>;
1901 #reset-cells = <1>;
1902 #power-domain-cells = <1>;
1904 clock-names = "xo";
1908 compatible = "arm,coresight-stm", "arm,primecell";
1911 reg-names = "stm-base", "stm-stimulus-base";
1914 clock-names = "apb_pclk";
1916 out-ports {
1919 remote-endpoint =
1927 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1931 clock-names = "apb_pclk";
1933 out-ports {
1936 remote-endpoint =
1942 in-ports {
1943 #address-cells = <1>;
1944 #size-cells = <0>;
1949 remote-endpoint = <&stm_out>;
1956 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1960 clock-names = "apb_pclk";
1962 out-ports {
1965 remote-endpoint =
1971 in-ports {
1972 #address-cells = <1>;
1973 #size-cells = <0>;
1978 remote-endpoint =
1986 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1990 clock-names = "apb_pclk";
1992 out-ports {
1995 remote-endpoint = <&etf_in>;
2000 in-ports {
2001 #address-cells = <1>;
2002 #size-cells = <0>;
2007 remote-endpoint =
2015 remote-endpoint =
2023 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2027 clock-names = "apb_pclk";
2029 out-ports {
2032 remote-endpoint = <&etr_in>;
2037 in-ports {
2040 remote-endpoint = <&etf_out>;
2047 compatible = "arm,coresight-tmc", "arm,primecell";
2051 clock-names = "apb_pclk";
2053 out-ports {
2056 remote-endpoint =
2062 in-ports {
2063 #address-cells = <1>;
2064 #size-cells = <0>;
2069 remote-endpoint =
2077 compatible = "arm,coresight-tmc", "arm,primecell";
2081 clock-names = "apb_pclk";
2082 arm,scatter-gather;
2084 in-ports {
2087 remote-endpoint =
2095 compatible = "arm,coresight-etm4x", "arm,primecell";
2101 clock-names = "apb_pclk";
2103 out-ports {
2106 remote-endpoint =
2114 compatible = "arm,coresight-etm4x", "arm,primecell";
2120 clock-names = "apb_pclk";
2122 out-ports {
2125 remote-endpoint =
2133 compatible = "arm,coresight-etm4x", "arm,primecell";
2139 clock-names = "apb_pclk";
2141 out-ports {
2144 remote-endpoint =
2152 compatible = "arm,coresight-etm4x", "arm,primecell";
2158 clock-names = "apb_pclk";
2160 out-ports {
2163 remote-endpoint =
2171 compatible = "arm,coresight-etm4x", "arm,primecell";
2177 clock-names = "apb_pclk";
2179 out-ports {
2182 remote-endpoint =
2190 compatible = "arm,coresight-etm4x", "arm,primecell";
2196 clock-names = "apb_pclk";
2198 out-ports {
2201 remote-endpoint =
2209 compatible = "arm,coresight-etm4x", "arm,primecell";
2215 clock-names = "apb_pclk";
2217 out-ports {
2220 remote-endpoint =
2228 compatible = "arm,coresight-etm4x", "arm,primecell";
2234 clock-names = "apb_pclk";
2236 out-ports {
2239 remote-endpoint =
2247 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2251 clock-names = "apb_pclk";
2253 out-ports {
2256 remote-endpoint =
2262 in-ports {
2263 #address-cells = <1>;
2264 #size-cells = <0>;
2269 remote-endpoint =
2277 remote-endpoint =
2285 remote-endpoint =
2293 remote-endpoint =
2301 remote-endpoint =
2309 remote-endpoint =
2317 remote-endpoint =
2325 remote-endpoint =
2333 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 clock-names = "apb_pclk";
2339 out-ports {
2342 remote-endpoint =
2348 in-ports {
2351 remote-endpoint =
2359 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
2364 interrupt-names = "hc_irq", "pwr_irq";
2368 clock-names = "iface", "core";
2375 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
2377 #address-cells = <1>;
2378 #size-cells = <0>;
2382 clock-names = "iface", "core";
2387 compatible = "qcom,sdm845-qusb2-phy";
2390 #phy-cells = <0>;
2394 clock-names = "cfg_ahb", "ref";
2398 nvmem-cells = <&qusb2p_hstx_trim>;
2402 compatible = "qcom,sdm845-qusb2-phy";
2405 #phy-cells = <0>;
2409 clock-names = "cfg_ahb", "ref";
2413 nvmem-cells = <&qusb2s_hstx_trim>;
2417 compatible = "qcom,sdm845-qmp-usb3-phy";
2420 reg-names = "reg-base", "dp_com";
2422 #clock-cells = <1>;
2423 #address-cells = <2>;
2424 #size-cells = <2>;
2431 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2435 reset-names = "phy", "common";
2444 #phy-cells = <0>;
2446 clock-names = "pipe0";
2447 clock-output-names = "usb3_phy_pipe_clk_src";
2452 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
2455 #clock-cells = <1>;
2456 #address-cells = <2>;
2457 #size-cells = <2>;
2464 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2468 reset-names = "phy", "common";
2475 #phy-cells = <0>;
2477 clock-names = "pipe0";
2478 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2483 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
2486 #address-cells = <2>;
2487 #size-cells = <2>;
2489 dma-ranges;
2496 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2499 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2501 assigned-clock-rates = <19200000>, <150000000>;
2507 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2510 power-domains = <&gcc USB30_PRIM_GDSC>;
2522 phy-names = "usb2-phy", "usb3-phy";
2527 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
2530 #address-cells = <2>;
2531 #size-cells = <2>;
2533 dma-ranges;
2540 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2543 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2545 assigned-clock-rates = <19200000>, <150000000>;
2551 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2554 power-domains = <&gcc USB30_SEC_GDSC>;
2566 phy-names = "usb2-phy", "usb3-phy";
2570 video-codec@aa00000 {
2571 compatible = "qcom,sdm845-venus";
2574 power-domains = <&videocc VENUS_GDSC>;
2578 clock-names = "core", "iface", "bus";
2581 memory-region = <&venus_mem>;
2583 video-core0 {
2584 compatible = "venus-decoder";
2587 clock-names = "core", "bus";
2588 power-domains = <&videocc VCODEC0_GDSC>;
2591 video-core1 {
2592 compatible = "venus-encoder";
2595 clock-names = "core", "bus";
2596 power-domains = <&videocc VCODEC1_GDSC>;
2600 videocc: clock-controller@ab00000 {
2601 compatible = "qcom,sdm845-videocc";
2603 #clock-cells = <1>;
2604 #power-domain-cells = <1>;
2605 #reset-cells = <1>;
2609 compatible = "qcom,sdm845-mdss";
2611 reg-names = "mdss";
2613 power-domains = <&dispcc MDSS_GDSC>;
2618 clock-names = "iface", "bus", "core";
2620 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2621 assigned-clock-rates = <300000000>;
2624 interrupt-controller;
2625 #interrupt-cells = <1>;
2632 #address-cells = <2>;
2633 #size-cells = <2>;
2637 compatible = "qcom,sdm845-dpu";
2640 reg-names = "mdp", "vbif";
2646 clock-names = "iface", "bus", "core", "vsync";
2648 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2650 assigned-clock-rates = <300000000>,
2653 interrupt-parent = <&mdss>;
2659 #address-cells = <1>;
2660 #size-cells = <0>;
2665 remote-endpoint = <&dsi0_in>;
2672 remote-endpoint = <&dsi1_in>;
2679 compatible = "qcom,mdss-dsi-ctrl";
2681 reg-names = "dsi_ctrl";
2683 interrupt-parent = <&mdss>;
2692 clock-names = "byte",
2700 phy-names = "dsi";
2705 #address-cells = <1>;
2706 #size-cells = <0>;
2711 remote-endpoint = <&dpu_intf1_out>;
2723 dsi0_phy: dsi-phy@ae94400 {
2724 compatible = "qcom,dsi-phy-10nm";
2728 reg-names = "dsi_phy",
2732 #clock-cells = <1>;
2733 #phy-cells = <0>;
2737 clock-names = "iface", "ref";
2743 compatible = "qcom,mdss-dsi-ctrl";
2745 reg-names = "dsi_ctrl";
2747 interrupt-parent = <&mdss>;
2756 clock-names = "byte",
2764 phy-names = "dsi";
2769 #address-cells = <1>;
2770 #size-cells = <0>;
2775 remote-endpoint = <&dpu_intf2_out>;
2787 dsi1_phy: dsi-phy@ae96400 {
2788 compatible = "qcom,dsi-phy-10nm";
2792 reg-names = "dsi_phy",
2796 #clock-cells = <1>;
2797 #phy-cells = <0>;
2801 clock-names = "iface", "ref";
2808 compatible = "qcom,adreno-630.2", "qcom,adreno";
2809 #stream-id-cells = <16>;
2812 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
2823 operating-points-v2 = <&gpu_opp_table>;
2827 zap-shader {
2828 memory-region = <&gpu_mem>;
2831 gpu_opp_table: opp-table {
2832 compatible = "operating-points-v2";
2834 opp-710000000 {
2835 opp-hz = /bits/ 64 <710000000>;
2836 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2839 opp-675000000 {
2840 opp-hz = /bits/ 64 <675000000>;
2841 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2844 opp-596000000 {
2845 opp-hz = /bits/ 64 <596000000>;
2846 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2849 opp-520000000 {
2850 opp-hz = /bits/ 64 <520000000>;
2851 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2854 opp-414000000 {
2855 opp-hz = /bits/ 64 <414000000>;
2856 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2859 opp-342000000 {
2860 opp-hz = /bits/ 64 <342000000>;
2861 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2864 opp-257000000 {
2865 opp-hz = /bits/ 64 <257000000>;
2866 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2872 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
2874 #iommu-cells = <1>;
2875 #global-interrupts = <2>;
2888 clock-names = "bus", "iface";
2890 power-domains = <&gpucc GPU_CX_GDSC>;
2894 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
2899 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2903 interrupt-names = "hfi", "gmu";
2909 clock-names = "gmu", "cxo", "axi", "memnoc";
2911 power-domains = <&gpucc GPU_CX_GDSC>,
2913 power-domain-names = "cx", "gx";
2917 operating-points-v2 = <&gmu_opp_table>;
2919 gmu_opp_table: opp-table {
2920 compatible = "operating-points-v2";
2922 opp-400000000 {
2923 opp-hz = /bits/ 64 <400000000>;
2924 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2927 opp-200000000 {
2928 opp-hz = /bits/ 64 <200000000>;
2929 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2934 dispcc: clock-controller@af00000 {
2935 compatible = "qcom,sdm845-dispcc";
2937 #clock-cells = <1>;
2938 #reset-cells = <1>;
2939 #power-domain-cells = <1>;
2942 pdc_reset: reset-controller@b2e0000 {
2943 compatible = "qcom,sdm845-pdc-global";
2945 #reset-cells = <1>;
2948 tsens0: thermal-sensor@c263000 {
2949 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
2953 #thermal-sensor-cells = <1>;
2956 tsens1: thermal-sensor@c265000 {
2957 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
2961 #thermal-sensor-cells = <1>;
2964 aoss_reset: reset-controller@c2a0000 {
2965 compatible = "qcom,sdm845-aoss-cc";
2967 #reset-cells = <1>;
2971 compatible = "qcom,sdm845-aoss-qmp";
2976 #clock-cells = <0>;
2977 #power-domain-cells = <1>;
2980 #cooling-cells = <2>;
2984 #cooling-cells = <2>;
2989 compatible = "qcom,spmi-pmic-arb";
2995 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2996 interrupt-names = "periph_irq";
3000 #address-cells = <2>;
3001 #size-cells = <0>;
3002 interrupt-controller;
3003 #interrupt-cells = <4>;
3004 cell-index = <0>;
3008 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
3010 #iommu-cells = <2>;
3011 #global-interrupts = <1>;
3079 lpasscc: clock-controller@17014000 {
3080 compatible = "qcom,sdm845-lpasscc";
3082 reg-names = "cc", "qdsp6ss";
3083 #clock-cells = <1>;
3088 compatible = "qcom,sdm845-apss-shared";
3090 #mbox-cells = <1>;
3095 compatible = "qcom,rpmh-rsc";
3099 reg-names = "drv-0", "drv-1", "drv-2";
3103 qcom,tcs-offset = <0xd00>;
3104 qcom,drv-id = <2>;
3105 qcom,tcs-config = <ACTIVE_TCS 2>,
3110 rpmhcc: clock-controller {
3111 compatible = "qcom,sdm845-rpmh-clk";
3112 #clock-cells = <1>;
3113 clock-names = "xo";
3117 rpmhpd: power-controller {
3118 compatible = "qcom,sdm845-rpmhpd";
3119 #power-domain-cells = <1>;
3120 operating-points-v2 = <&rpmhpd_opp_table>;
3122 rpmhpd_opp_table: opp-table {
3123 compatible = "operating-points-v2";
3126 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3130 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3134 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3138 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3142 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3146 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3150 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3154 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3158 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3162 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3168 compatible = "qcom,sdm845-rsc-hlos";
3169 #interconnect-cells = <1>;
3173 intc: interrupt-controller@17a00000 {
3174 compatible = "arm,gic-v3";
3175 #address-cells = <2>;
3176 #size-cells = <2>;
3178 #interrupt-cells = <3>;
3179 interrupt-controller;
3184 gic-its@17a40000 {
3185 compatible = "arm,gic-v3-its";
3186 msi-controller;
3187 #msi-cells = <1>;
3194 #address-cells = <2>;
3195 #size-cells = <2>;
3197 compatible = "arm,armv7-timer-mem";
3201 frame-number = <0>;
3209 frame-number = <1>;
3216 frame-number = <2>;
3223 frame-number = <3>;
3230 frame-number = <4>;
3237 frame-number = <5>;
3244 frame-number = <6>;
3252 compatible = "qcom,cpufreq-hw";
3254 reg-names = "freq-domain0", "freq-domain1";
3257 clock-names = "xo", "alternate";
3259 #freq-domain-cells = <1>;
3263 compatible = "qcom,wcn3990-wifi";
3266 reg-names = "membase";
3267 memory-region = <&wlan_msa_mem>;
3268 clock-names = "cxo_ref_clk_pin";
3287 thermal-zones {
3288 cpu0-thermal {
3289 polling-delay-passive = <250>;
3290 polling-delay = <1000>;
3292 thermal-sensors = <&tsens0 1>;
3295 cpu0_alert0: trip-point0 {
3301 cpu0_alert1: trip-point1 {
3314 cooling-maps {
3317 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3324 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3332 cpu1-thermal {
3333 polling-delay-passive = <250>;
3334 polling-delay = <1000>;
3336 thermal-sensors = <&tsens0 2>;
3339 cpu1_alert0: trip-point0 {
3345 cpu1_alert1: trip-point1 {
3358 cooling-maps {
3361 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3368 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3376 cpu2-thermal {
3377 polling-delay-passive = <250>;
3378 polling-delay = <1000>;
3380 thermal-sensors = <&tsens0 3>;
3383 cpu2_alert0: trip-point0 {
3389 cpu2_alert1: trip-point1 {
3402 cooling-maps {
3405 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3412 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3420 cpu3-thermal {
3421 polling-delay-passive = <250>;
3422 polling-delay = <1000>;
3424 thermal-sensors = <&tsens0 4>;
3427 cpu3_alert0: trip-point0 {
3433 cpu3_alert1: trip-point1 {
3446 cooling-maps {
3449 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3456 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3464 cpu4-thermal {
3465 polling-delay-passive = <250>;
3466 polling-delay = <1000>;
3468 thermal-sensors = <&tsens0 7>;
3471 cpu4_alert0: trip-point0 {
3477 cpu4_alert1: trip-point1 {
3490 cooling-maps {
3493 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3500 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3508 cpu5-thermal {
3509 polling-delay-passive = <250>;
3510 polling-delay = <1000>;
3512 thermal-sensors = <&tsens0 8>;
3515 cpu5_alert0: trip-point0 {
3521 cpu5_alert1: trip-point1 {
3534 cooling-maps {
3537 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3544 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3552 cpu6-thermal {
3553 polling-delay-passive = <250>;
3554 polling-delay = <1000>;
3556 thermal-sensors = <&tsens0 9>;
3559 cpu6_alert0: trip-point0 {
3565 cpu6_alert1: trip-point1 {
3578 cooling-maps {
3581 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3588 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3596 cpu7-thermal {
3597 polling-delay-passive = <250>;
3598 polling-delay = <1000>;
3600 thermal-sensors = <&tsens0 10>;
3603 cpu7_alert0: trip-point0 {
3609 cpu7_alert1: trip-point1 {
3622 cooling-maps {
3625 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3632 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3640 aoss0-thermal {
3641 polling-delay-passive = <250>;
3642 polling-delay = <1000>;
3644 thermal-sensors = <&tsens0 0>;
3647 aoss0_alert0: trip-point0 {
3655 cluster0-thermal {
3656 polling-delay-passive = <250>;
3657 polling-delay = <1000>;
3659 thermal-sensors = <&tsens0 5>;
3662 cluster0_alert0: trip-point0 {
3675 cluster1-thermal {
3676 polling-delay-passive = <250>;
3677 polling-delay = <1000>;
3679 thermal-sensors = <&tsens0 6>;
3682 cluster1_alert0: trip-point0 {
3695 gpu-thermal-top {
3696 polling-delay-passive = <250>;
3697 polling-delay = <1000>;
3699 thermal-sensors = <&tsens0 11>;
3702 gpu1_alert0: trip-point0 {
3710 gpu-thermal-bottom {
3711 polling-delay-passive = <250>;
3712 polling-delay = <1000>;
3714 thermal-sensors = <&tsens0 12>;
3717 gpu2_alert0: trip-point0 {
3725 aoss1-thermal {
3726 polling-delay-passive = <250>;
3727 polling-delay = <1000>;
3729 thermal-sensors = <&tsens1 0>;
3732 aoss1_alert0: trip-point0 {
3740 q6-modem-thermal {
3741 polling-delay-passive = <250>;
3742 polling-delay = <1000>;
3744 thermal-sensors = <&tsens1 1>;
3747 q6_modem_alert0: trip-point0 {
3755 mem-thermal {
3756 polling-delay-passive = <250>;
3757 polling-delay = <1000>;
3759 thermal-sensors = <&tsens1 2>;
3762 mem_alert0: trip-point0 {
3770 wlan-thermal {
3771 polling-delay-passive = <250>;
3772 polling-delay = <1000>;
3774 thermal-sensors = <&tsens1 3>;
3777 wlan_alert0: trip-point0 {
3785 q6-hvx-thermal {
3786 polling-delay-passive = <250>;
3787 polling-delay = <1000>;
3789 thermal-sensors = <&tsens1 4>;
3792 q6_hvx_alert0: trip-point0 {
3800 camera-thermal {
3801 polling-delay-passive = <250>;
3802 polling-delay = <1000>;
3804 thermal-sensors = <&tsens1 5>;
3807 camera_alert0: trip-point0 {
3815 video-thermal {
3816 polling-delay-passive = <250>;
3817 polling-delay = <1000>;
3819 thermal-sensors = <&tsens1 6>;
3822 video_alert0: trip-point0 {
3830 modem-thermal {
3831 polling-delay-passive = <250>;
3832 polling-delay = <1000>;
3834 thermal-sensors = <&tsens1 7>;
3837 modem_alert0: trip-point0 {