Lines Matching refs:gcc
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
256 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
282 clocks = <&gcc GCC_PRNG_AHB_CLK>;
309 <&gcc GCC_CDSP_CFG_AHB_CLK>,
310 <&gcc GCC_CDSP_TBU_CLK>,
311 <&gcc GCC_BIMC_CDSP_CLK>,
325 resets = <&gcc GCC_CDSP_RESTART>;
460 gcc: clock-controller@1800000 { label
461 compatible = "qcom,gcc-qcs404";
466 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
534 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
535 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
536 <&gcc 21>;
554 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
555 <&gcc GCC_SDCC1_AHB_CLK>,
566 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
577 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
590 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
603 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
618 clocks = <&gcc GCC_ETH_AXI_CLK>,
619 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
620 <&gcc GCC_ETH_PTP_CLK>,
621 <&gcc GCC_ETH_RGMII_CLK>;
657 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
670 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
671 <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
684 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
685 <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
698 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
699 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
712 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
713 <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
726 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
727 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
740 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
741 <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
754 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
755 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
768 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
769 <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
782 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
783 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
796 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
797 <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
810 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
821 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
834 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
835 <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
848 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
849 <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
988 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
989 <&gcc GCC_PCIE_0_AUX_CLK>,
990 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
991 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
994 resets = <&gcc 18>,
995 <&gcc 17>,
996 <&gcc 15>,
997 <&gcc 19>,
998 <&gcc GCC_PCIE_0_BCR>,
999 <&gcc 16>;