Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/thermal/thermal.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
20 xo_board: xo-board {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <19200000>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a53";
35 enable-method = "psci";
36 cpu-idle-states = <&CPU_SLEEP_0>;
37 next-level-cache = <&L2_0>;
38 #cooling-cells = <2>;
43 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 cpu-idle-states = <&CPU_SLEEP_0>;
47 next-level-cache = <&L2_0>;
48 #cooling-cells = <2>;
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
57 next-level-cache = <&L2_0>;
58 #cooling-cells = <2>;
63 compatible = "arm,cortex-a53";
65 enable-method = "psci";
66 cpu-idle-states = <&CPU_SLEEP_0>;
67 next-level-cache = <&L2_0>;
68 #cooling-cells = <2>;
71 L2_0: l2-cache {
73 cache-level = <2>;
76 idle-states {
77 entry-method = "psci";
79 CPU_SLEEP_0: cpu-sleep-0 {
80 compatible = "arm,idle-state";
81 idle-state-name = "standalone-power-collapse";
82 arm,psci-suspend-param = <0x40000003>;
83 entry-latency-us = <125>;
84 exit-latency-us = <180>;
85 min-residency-us = <595>;
86 local-timer-stop;
93 compatible = "qcom,scm-qcs404", "qcom,scm";
94 #reset-cells = <1>;
104 psci {
105 compatible = "arm,psci-1.0";
109 reserved-memory {
110 #address-cells = <2>;
111 #size-cells = <2>;
116 no-map;
121 no-map;
126 no-map;
131 no-map;
136 no-map;
141 no-map;
146 no-map;
151 no-map;
156 no-map;
160 rpm-glink {
161 compatible = "qcom,glink-rpm";
164 qcom,rpm-msg-ram = <&rpm_msg_ram>;
167 rpm_requests: glink-channel {
168 compatible = "qcom,rpm-qcs404";
169 qcom,glink-channels = "rpm_requests";
171 rpmcc: clock-controller {
172 compatible = "qcom,rpmcc-qcs404";
173 #clock-cells = <1>;
176 rpmpd: power-controller {
177 compatible = "qcom,qcs404-rpmpd";
178 #power-domain-cells = <1>;
179 operating-points-v2 = <&rpmpd_opp_table>;
181 rpmpd_opp_table: opp-table {
182 compatible = "operating-points-v2";
185 opp-level = <16>;
189 opp-level = <32>;
193 opp-level = <48>;
197 opp-level = <64>;
201 opp-level = <128>;
205 opp-level = <192>;
209 opp-level = <256>;
213 opp-level = <320>;
217 opp-level = <384>;
221 opp-level = <416>;
225 opp-level = <512>;
235 memory-region = <&smem_region>;
236 qcom,rpm-msg-ram = <&rpm_msg_ram>;
242 compatible = "qcom,tcsr-mutex";
244 #hwlock-cells = <1>;
248 #address-cells = <1>;
249 #size-cells = <1>;
251 compatible = "simple-bus";
253 turingcc: clock-controller@800000 {
254 compatible = "qcom,qcs404-turingcc";
258 #clock-cells = <1>;
259 #reset-cells = <1>;
265 compatible = "qcom,rpm-msg-ram";
272 #address-cells = <1>;
273 #size-cells = <1>;
280 compatible = "qcom,prng-ee";
283 clock-names = "core";
286 tsens: thermal-sensor@4a9000 {
287 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
290 nvmem-cells = <&tsens_caldata>;
291 nvmem-cell-names = "calib";
293 #thermal-sensor-cells = <1>;
297 compatible = "qcom,qcs404-cdsp-pas";
300 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
305 interrupt-names = "wdog", "fatal", "ready",
306 "handover", "stop-ack";
316 clock-names = "xo",
326 reset-names = "restart";
328 qcom,halt-regs = <&tcsr 0x19004>;
330 memory-region = <&cdsp_fw_mem>;
332 qcom,smem-states = <&cdsp_smp2p_out 0>;
333 qcom,smem-state-names = "stop";
337 glink-edge {
340 qcom,remote-pid = <5>;
348 compatible = "qcom,qcs404-pinctrl";
352 reg-names = "south", "north", "east";
354 gpio-ranges = <&tlmm 0 0 120>;
355 gpio-controller;
356 #gpio-cells = <2>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
360 blsp1_i2c0_default: blsp1-i2c0-default {
365 blsp1_i2c1_default: blsp1-i2c1-default {
370 blsp1_i2c2_default: blsp1-i2c2-default {
382 blsp1_i2c3_default: blsp1-i2c3-default {
387 blsp1_i2c4_default: blsp1-i2c4-default {
392 blsp1_uart0_default: blsp1-uart0-default {
397 blsp1_uart1_default: blsp1-uart1-default {
402 blsp1_uart2_default: blsp1-uart2-default {
414 blsp1_uart3_default: blsp1-uart3-default {
419 blsp2_i2c0_default: blsp2-i2c0-default {
424 blsp1_spi0_default: blsp1-spi0-default {
429 blsp1_spi1_default: blsp1-spi1-default {
434 blsp1_spi2_default: blsp1-spi2-default {
439 blsp1_spi3_default: blsp1-spi3-default {
444 blsp1_spi4_default: blsp1-spi4-default {
449 blsp2_spi0_default: blsp2-spi0-default {
454 blsp2_uart0_default: blsp2-uart0-default {
460 gcc: clock-controller@1800000 {
461 compatible = "qcom,gcc-qcs404";
463 #clock-cells = <1>;
464 #reset-cells = <1>;
466 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
467 assigned-clock-rates = <19200000>;
481 compatible = "qcom,spmi-pmic-arb";
487 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
488 interrupt-names = "periph_irq";
492 #address-cells = <2>;
493 #size-cells = <0>;
494 interrupt-controller;
495 #interrupt-cells = <4>;
499 compatible = "qcom,qcs404-wcss-pas";
502 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
507 interrupt-names = "wdog", "fatal", "ready",
508 "handover", "stop-ack";
511 clock-names = "xo";
513 memory-region = <&wlan_fw_mem>;
515 qcom,smem-states = <&wcss_smp2p_out 0>;
516 qcom,smem-state-names = "stop";
520 glink-edge {
523 qcom,remote-pid = <1>;
531 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
537 reset-names = "phy", "pipe";
539 clock-output-names = "pcie_0_pipe_clk";
540 #phy-cells = <0>;
546 compatible = "qcom,sdhci-msm-v5";
548 reg-names = "hc_mem", "cmdq_mem";
552 interrupt-names = "hc_irq", "pwr_irq";
557 clock-names = "core", "iface", "xo";
563 compatible = "qcom,bam-v1.7.0";
567 clock-names = "bam_clk";
568 #dma-cells = <1>;
574 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
578 clock-names = "core", "iface";
580 dma-names = "rx", "tx";
581 pinctrl-names = "default";
582 pinctrl-0 = <&blsp1_uart0_default>;
587 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
591 clock-names = "core", "iface";
593 dma-names = "rx", "tx";
594 pinctrl-names = "default";
595 pinctrl-0 = <&blsp1_uart1_default>;
600 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
604 clock-names = "core", "iface";
606 dma-names = "rx", "tx";
607 pinctrl-names = "default";
608 pinctrl-0 = <&blsp1_uart2_default>;
613 compatible = "qcom,qcs404-ethqos";
616 reg-names = "stmmaceth", "rgmii";
617 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
624 interrupt-names = "macirq", "eth_lpi";
627 rx-fifo-depth = <4096>;
628 tx-fifo-depth = <4096>;
634 compatible = "qcom,wcn3990-wifi";
636 reg-names = "membase";
637 memory-region = <&wlan_msa_mem>;
654 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
658 clock-names = "core", "iface";
660 dma-names = "rx", "tx";
661 pinctrl-names = "default";
662 pinctrl-0 = <&blsp1_uart3_default>;
667 compatible = "qcom,i2c-qup-v2.2.1";
672 clock-names = "iface", "core";
673 pinctrl-names = "default";
674 pinctrl-0 = <&blsp1_i2c0_default>;
675 #address-cells = <1>;
676 #size-cells = <0>;
681 compatible = "qcom,spi-qup-v2.2.1";
686 clock-names = "iface", "core";
687 pinctrl-names = "default";
688 pinctrl-0 = <&blsp1_spi0_default>;
689 #address-cells = <1>;
690 #size-cells = <0>;
695 compatible = "qcom,i2c-qup-v2.2.1";
700 clock-names = "iface", "core";
701 pinctrl-names = "default";
702 pinctrl-0 = <&blsp1_i2c1_default>;
703 #address-cells = <1>;
704 #size-cells = <0>;
709 compatible = "qcom,spi-qup-v2.2.1";
714 clock-names = "iface", "core";
715 pinctrl-names = "default";
716 pinctrl-0 = <&blsp1_spi1_default>;
717 #address-cells = <1>;
718 #size-cells = <0>;
723 compatible = "qcom,i2c-qup-v2.2.1";
728 clock-names = "iface", "core";
729 pinctrl-names = "default";
730 pinctrl-0 = <&blsp1_i2c2_default>;
731 #address-cells = <1>;
732 #size-cells = <0>;
737 compatible = "qcom,spi-qup-v2.2.1";
742 clock-names = "iface", "core";
743 pinctrl-names = "default";
744 pinctrl-0 = <&blsp1_spi2_default>;
745 #address-cells = <1>;
746 #size-cells = <0>;
751 compatible = "qcom,i2c-qup-v2.2.1";
756 clock-names = "iface", "core";
757 pinctrl-names = "default";
758 pinctrl-0 = <&blsp1_i2c3_default>;
759 #address-cells = <1>;
760 #size-cells = <0>;
765 compatible = "qcom,spi-qup-v2.2.1";
770 clock-names = "iface", "core";
771 pinctrl-names = "default";
772 pinctrl-0 = <&blsp1_spi3_default>;
773 #address-cells = <1>;
774 #size-cells = <0>;
779 compatible = "qcom,i2c-qup-v2.2.1";
784 clock-names = "iface", "core";
785 pinctrl-names = "default";
786 pinctrl-0 = <&blsp1_i2c4_default>;
787 #address-cells = <1>;
788 #size-cells = <0>;
793 compatible = "qcom,spi-qup-v2.2.1";
798 clock-names = "iface", "core";
799 pinctrl-names = "default";
800 pinctrl-0 = <&blsp1_spi4_default>;
801 #address-cells = <1>;
802 #size-cells = <0>;
807 compatible = "qcom,bam-v1.7.0";
811 clock-names = "bam_clk";
812 #dma-cells = <1>;
818 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
822 clock-names = "core", "iface";
824 dma-names = "rx", "tx";
825 pinctrl-names = "default";
826 pinctrl-0 = <&blsp2_uart0_default>;
831 compatible = "qcom,i2c-qup-v2.2.1";
836 clock-names = "iface", "core";
837 pinctrl-names = "default";
838 pinctrl-0 = <&blsp2_i2c0_default>;
839 #address-cells = <1>;
840 #size-cells = <0>;
845 compatible = "qcom,spi-qup-v2.2.1";
850 clock-names = "iface", "core";
851 pinctrl-names = "default";
852 pinctrl-0 = <&blsp2_spi0_default>;
853 #address-cells = <1>;
854 #size-cells = <0>;
858 intc: interrupt-controller@b000000 {
859 compatible = "qcom,msm-qgic2";
860 interrupt-controller;
861 #interrupt-cells = <3>;
867 compatible = "qcom,qcs404-apcs-apps-global", "syscon";
869 #mbox-cells = <1>;
873 #address-cells = <1>;
874 #size-cells = <1>;
876 compatible = "arm,armv7-timer-mem";
878 clock-frequency = <19200000>;
881 frame-number = <0>;
889 frame-number = <1>;
896 frame-number = <2>;
903 frame-number = <3>;
910 frame-number = <4>;
917 frame-number = <5>;
924 frame-number = <6>;
932 compatible = "qcom,qcs404-adsp-pas";
935 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
940 interrupt-names = "wdog", "fatal", "ready",
941 "handover", "stop-ack";
944 clock-names = "xo";
946 memory-region = <&adsp_fw_mem>;
948 qcom,smem-states = <&adsp_smp2p_out 0>;
949 qcom,smem-state-names = "stop";
953 glink-edge {
956 qcom,remote-pid = <2>;
964 compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
969 reg-names = "dbi", "elbi", "parf", "config";
971 linux,pci-domain = <0>;
972 bus-range = <0x00 0xff>;
973 num-lanes = <1>;
974 #address-cells = <3>;
975 #size-cells = <2>;
981 interrupt-names = "msi";
982 #interrupt-cells = <1>;
983 interrupt-map-mask = <0 0 0 0x7>;
984 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
992 clock-names = "iface", "aux", "master_bus", "slave_bus";
1000 reset-names = "axi_m",
1008 phy-names = "pciephy";
1015 compatible = "arm,armv8-timer";
1022 smp2p-adsp {
1027 qcom,local-pid = <0>;
1028 qcom,remote-pid = <2>;
1030 adsp_smp2p_out: master-kernel {
1031 qcom,entry-name = "master-kernel";
1032 #qcom,smem-state-cells = <1>;
1035 adsp_smp2p_in: slave-kernel {
1036 qcom,entry-name = "slave-kernel";
1037 interrupt-controller;
1038 #interrupt-cells = <2>;
1042 smp2p-cdsp {
1047 qcom,local-pid = <0>;
1048 qcom,remote-pid = <5>;
1050 cdsp_smp2p_out: master-kernel {
1051 qcom,entry-name = "master-kernel";
1052 #qcom,smem-state-cells = <1>;
1055 cdsp_smp2p_in: slave-kernel {
1056 qcom,entry-name = "slave-kernel";
1057 interrupt-controller;
1058 #interrupt-cells = <2>;
1062 smp2p-wcss {
1067 qcom,local-pid = <0>;
1068 qcom,remote-pid = <1>;
1070 wcss_smp2p_out: master-kernel {
1071 qcom,entry-name = "master-kernel";
1072 #qcom,smem-state-cells = <1>;
1075 wcss_smp2p_in: slave-kernel {
1076 qcom,entry-name = "slave-kernel";
1077 interrupt-controller;
1078 #interrupt-cells = <2>;
1082 thermal-zones {
1083 aoss-thermal {
1084 polling-delay-passive = <250>;
1085 polling-delay = <1000>;
1087 thermal-sensors = <&tsens 0>;
1090 aoss_alert0: trip-point0 {
1098 q6-hvx-thermal {
1099 polling-delay-passive = <250>;
1100 polling-delay = <1000>;
1102 thermal-sensors = <&tsens 1>;
1105 q6_hvx_alert0: trip-point0 {
1113 lpass-thermal {
1114 polling-delay-passive = <250>;
1115 polling-delay = <1000>;
1117 thermal-sensors = <&tsens 2>;
1120 lpass_alert0: trip-point0 {
1128 wlan-thermal {
1129 polling-delay-passive = <250>;
1130 polling-delay = <1000>;
1132 thermal-sensors = <&tsens 3>;
1135 wlan_alert0: trip-point0 {
1143 cluster-thermal {
1144 polling-delay-passive = <250>;
1145 polling-delay = <1000>;
1147 thermal-sensors = <&tsens 4>;
1150 cluster_alert0: trip-point0 {
1155 cluster_alert1: trip-point1 {
1166 cooling-maps {
1169 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1177 cpu0-thermal {
1178 polling-delay-passive = <250>;
1179 polling-delay = <1000>;
1181 thermal-sensors = <&tsens 5>;
1184 cpu0_alert0: trip-point0 {
1189 cpu0_alert1: trip-point1 {
1200 cooling-maps {
1203 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1211 cpu1-thermal {
1212 polling-delay-passive = <250>;
1213 polling-delay = <1000>;
1215 thermal-sensors = <&tsens 6>;
1218 cpu1_alert0: trip-point0 {
1223 cpu1_alert1: trip-point1 {
1234 cooling-maps {
1237 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1245 cpu2-thermal {
1246 polling-delay-passive = <250>;
1247 polling-delay = <1000>;
1249 thermal-sensors = <&tsens 7>;
1252 cpu2_alert0: trip-point0 {
1257 cpu2_alert1: trip-point1 {
1268 cooling-maps {
1271 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1279 cpu3-thermal {
1280 polling-delay-passive = <250>;
1281 polling-delay = <1000>;
1283 thermal-sensors = <&tsens 8>;
1286 cpu3_alert0: trip-point0 {
1291 cpu3_alert1: trip-point1 {
1302 cooling-maps {
1305 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1313 gpu-thermal {
1314 polling-delay-passive = <250>;
1315 polling-delay = <1000>;
1317 thermal-sensors = <&tsens 9>;
1320 gpu_alert0: trip-point0 {