Lines Matching refs:gcc
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
353 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
382 gcc: clock-controller@1800000 { label
383 compatible = "qcom,gcc-msm8916";
415 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
440 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
451 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
462 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
463 <&gcc GCC_BLSP1_AHB_CLK>;
479 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
480 <&gcc GCC_BLSP1_AHB_CLK>;
496 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
497 <&gcc GCC_BLSP1_AHB_CLK>;
513 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
514 <&gcc GCC_BLSP1_AHB_CLK>;
530 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
531 <&gcc GCC_BLSP1_AHB_CLK>;
547 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
548 <&gcc GCC_BLSP1_AHB_CLK>;
564 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
565 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
579 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
580 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
594 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
595 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
608 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
609 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
610 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
611 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
612 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
613 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
614 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
634 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
635 <&gcc GCC_CODEC_DIGCODEC_CLK>;
647 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
648 <&gcc GCC_SDCC1_AHB_CLK>,
664 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
665 <&gcc GCC_SDCC2_AHB_CLK>,
678 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
679 <&gcc GCC_USB_HS_SYSTEM_CLK>;
681 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
683 resets = <&gcc GCC_USB_HS_BCR>;
698 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
700 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
795 clocks = <&gcc GCC_PRNG_AHB_CLK>;
829 clocks = <&gcc GCC_SMMU_CFG_CLK>,
830 <&gcc GCC_APSS_TCU_CLK>;
862 clocks = <&gcc GCC_SMMU_CFG_CLK>,
863 <&gcc GCC_GFX_TCU_CLK>;
896 <&gcc GCC_OXILI_GFX3D_CLK>,
897 <&gcc GCC_OXILI_AHB_CLK>,
898 <&gcc GCC_OXILI_GMEM_CLK>,
899 <&gcc GCC_BIMC_GFX_CLK>,
900 <&gcc GCC_BIMC_GPU_CLK>,
901 <&gcc GFX3D_CLK_SRC>;
902 power-domains = <&gcc OXILI_GDSC>;
913 power-domains = <&gcc MDSS_GDSC>;
915 clocks = <&gcc GCC_MDSS_AHB_CLK>,
916 <&gcc GCC_MDSS_AXI_CLK>,
917 <&gcc GCC_MDSS_VSYNC_CLK>;
939 clocks = <&gcc GCC_MDSS_AHB_CLK>,
940 <&gcc GCC_MDSS_AXI_CLK>,
941 <&gcc GCC_MDSS_MDP_CLK>,
942 <&gcc GCC_MDSS_VSYNC_CLK>;
971 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
972 <&gcc PCLK0_CLK_SRC>;
976 clocks = <&gcc GCC_MDSS_MDP_CLK>,
977 <&gcc GCC_MDSS_AHB_CLK>,
978 <&gcc GCC_MDSS_AXI_CLK>,
979 <&gcc GCC_MDSS_BYTE0_CLK>,
980 <&gcc GCC_MDSS_PCLK0_CLK>,
981 <&gcc GCC_MDSS_ESC0_CLK>;
1022 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1044 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1045 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1046 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1436 power-domains = <&gcc VENUS_GDSC>;
1437 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1438 <&gcc GCC_VENUS0_AHB_CLK>,
1439 <&gcc GCC_VENUS0_AXI_CLK>;
1486 power-domains = <&gcc VFE_GDSC>;
1487 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1488 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1489 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1490 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1491 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1492 <&gcc GCC_CAMSS_CSI0_CLK>,
1493 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1494 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1495 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1496 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1497 <&gcc GCC_CAMSS_CSI1_CLK>,
1498 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1499 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1500 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1501 <&gcc GCC_CAMSS_AHB_CLK>,
1502 <&gcc GCC_CAMSS_VFE0_CLK>,
1503 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1504 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1505 <&gcc GCC_CAMSS_VFE_AXI_CLK>;