Lines Matching refs:gcc
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
142 gcc: gcc@1800000 { label
143 compatible = "qcom,gcc-ipq8074";
153 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
154 <&gcc GCC_BLSP1_AHB_CLK>;
165 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
175 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
176 <&gcc GCC_BLSP1_AHB_CLK>;
185 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
186 <&gcc GCC_BLSP1_AHB_CLK>;
203 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
204 <&gcc GCC_BLSP1_AHB_CLK>;
219 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
220 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
236 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
237 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
249 clocks = <&gcc GCC_QPIC_AHB_CLK>;
261 clocks = <&gcc GCC_QPIC_CLK>,
262 <&gcc GCC_QPIC_AHB_CLK>;
278 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
282 resets = <&gcc GCC_PCIE0_PHY_BCR>,
283 <&gcc GCC_PCIE0PHY_PHY_BCR>;
324 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
325 <&gcc GCC_PCIE0_AXI_M_CLK>,
326 <&gcc GCC_PCIE0_AXI_S_CLK>,
327 <&gcc GCC_PCIE0_AHB_CLK>,
328 <&gcc GCC_PCIE0_AUX_CLK>;
335 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
336 <&gcc GCC_PCIE0_SLEEP_ARES>,
337 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
338 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
339 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
340 <&gcc GCC_PCIE0_AHB_ARES>,
341 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
356 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
360 resets = <&gcc GCC_PCIE1_PHY_BCR>,
361 <&gcc GCC_PCIE1PHY_PHY_BCR>;
402 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
403 <&gcc GCC_PCIE1_AXI_M_CLK>,
404 <&gcc GCC_PCIE1_AXI_S_CLK>,
405 <&gcc GCC_PCIE1_AHB_CLK>,
406 <&gcc GCC_PCIE1_AUX_CLK>;
412 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
413 <&gcc GCC_PCIE1_SLEEP_ARES>,
414 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
415 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
416 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
417 <&gcc GCC_PCIE1_AHB_ARES>,
418 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;