Lines Matching +full:reset +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
25 compatible = "nvidia,tegra194-gpio";
26 reg-names = "security", "gpio";
35 #interrupt-cells = <2>;
36 interrupt-controller;
37 #gpio-cells = <2>;
38 gpio-controller;
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
51 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
53 reset-names = "eqos";
56 snps,write-requests = <1>;
57 snps,read-requests = <3>;
58 snps,burst-map = <0x7>;
64 compatible = "nvidia,tegra194-aconnect",
65 "nvidia,tegra210-aconnect";
68 clock-names = "ape", "apb2ape";
69 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
70 #address-cells = <1>;
71 #size-cells = <1>;
75 dma-controller@2930000 {
76 compatible = "nvidia,tegra194-adma",
77 "nvidia,tegra186-adma";
79 interrupt-parent = <&agic>;
112 #dma-cells = <1>;
114 clock-names = "d_audio";
118 agic: interrupt-controller@2a40000 {
119 compatible = "nvidia,tegra194-agic",
120 "nvidia,tegra210-agic";
121 #interrupt-cells = <3>;
122 interrupt-controller;
129 clock-names = "clk";
135 compatible = "nvidia,tegra194-pinmux";
146 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
147 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
158 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
159 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
167 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
169 reg-shift = <2>;
172 clock-names = "serial";
174 reset-names = "serial";
179 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
181 reg-shift = <2>;
184 clock-names = "serial";
186 reset-names = "serial";
191 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
193 reg-shift = <2>;
196 clock-names = "serial";
198 reset-names = "serial";
203 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
205 reg-shift = <2>;
208 clock-names = "serial";
210 reset-names = "serial";
215 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
217 reg-shift = <2>;
220 clock-names = "serial";
222 reset-names = "serial";
227 compatible = "nvidia,tegra194-i2c";
230 #address-cells = <1>;
231 #size-cells = <0>;
233 clock-names = "div-clk";
235 reset-names = "i2c";
240 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
242 reg-shift = <2>;
245 clock-names = "serial";
247 reset-names = "serial";
252 compatible = "nvidia,tegra194-i2c";
255 #address-cells = <1>;
256 #size-cells = <0>;
258 clock-names = "div-clk";
260 reset-names = "i2c";
266 compatible = "nvidia,tegra194-i2c";
269 #address-cells = <1>;
270 #size-cells = <0>;
272 clock-names = "div-clk";
274 reset-names = "i2c";
280 compatible = "nvidia,tegra194-i2c";
283 #address-cells = <1>;
284 #size-cells = <0>;
286 clock-names = "div-clk";
288 reset-names = "i2c";
293 compatible = "nvidia,tegra194-i2c";
296 #address-cells = <1>;
297 #size-cells = <0>;
299 clock-names = "div-clk";
301 reset-names = "i2c";
306 compatible = "nvidia,tegra194-i2c";
309 #address-cells = <1>;
310 #size-cells = <0>;
312 clock-names = "div-clk";
314 reset-names = "i2c";
319 compatible = "nvidia,tegra194-pwm",
320 "nvidia,tegra186-pwm";
323 clock-names = "pwm";
325 reset-names = "pwm";
327 #pwm-cells = <2>;
331 compatible = "nvidia,tegra194-pwm",
332 "nvidia,tegra186-pwm";
335 clock-names = "pwm";
337 reset-names = "pwm";
339 #pwm-cells = <2>;
343 compatible = "nvidia,tegra194-pwm",
344 "nvidia,tegra186-pwm";
347 clock-names = "pwm";
349 reset-names = "pwm";
351 #pwm-cells = <2>;
355 compatible = "nvidia,tegra194-pwm",
356 "nvidia,tegra186-pwm";
359 clock-names = "pwm";
361 reset-names = "pwm";
363 #pwm-cells = <2>;
367 compatible = "nvidia,tegra194-pwm",
368 "nvidia,tegra186-pwm";
371 clock-names = "pwm";
373 reset-names = "pwm";
375 #pwm-cells = <2>;
379 compatible = "nvidia,tegra194-pwm",
380 "nvidia,tegra186-pwm";
383 clock-names = "pwm";
385 reset-names = "pwm";
387 #pwm-cells = <2>;
391 compatible = "nvidia,tegra194-pwm",
392 "nvidia,tegra186-pwm";
395 clock-names = "pwm";
397 reset-names = "pwm";
399 #pwm-cells = <2>;
403 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
407 clock-names = "sdhci";
409 reset-names = "sdhci";
410 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
412 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
414 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
415 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
417 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
418 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
419 nvidia,default-tap = <0x9>;
420 nvidia,default-trim = <0x5>;
425 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
429 clock-names = "sdhci";
431 reset-names = "sdhci";
432 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
433 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
434 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
435 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
437 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
438 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
440 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
441 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
442 nvidia,default-tap = <0x9>;
443 nvidia,default-trim = <0x5>;
448 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
452 clock-names = "sdhci";
453 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
455 assigned-clock-parents =
458 reset-names = "sdhci";
459 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
460 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
461 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
462 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
464 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
465 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
467 nvidia,default-tap = <0x8>;
468 nvidia,default-trim = <0x14>;
469 nvidia,dqs-trim = <40>;
470 supports-cqe;
475 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
481 clock-names = "hda", "hda2codec_2x", "hda2hdmi";
485 reset-names = "hda", "hda2codec_2x", "hda2hdmi";
486 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
490 gic: interrupt-controller@3881000 {
491 compatible = "arm,gic-400";
492 #interrupt-cells = <3>;
493 interrupt-controller;
500 interrupt-parent = <&gic>;
504 compatible = "nvidia,tegra194-cec";
508 clock-names = "cec";
513 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
524 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
527 #mbox-cells = <2>;
531 compatible = "nvidia,tegra194-p2u";
533 reg-names = "ctl";
535 #phy-cells = <0>;
539 compatible = "nvidia,tegra194-p2u";
541 reg-names = "ctl";
543 #phy-cells = <0>;
547 compatible = "nvidia,tegra194-p2u";
549 reg-names = "ctl";
551 #phy-cells = <0>;
555 compatible = "nvidia,tegra194-p2u";
557 reg-names = "ctl";
559 #phy-cells = <0>;
563 compatible = "nvidia,tegra194-p2u";
565 reg-names = "ctl";
567 #phy-cells = <0>;
571 compatible = "nvidia,tegra194-p2u";
573 reg-names = "ctl";
575 #phy-cells = <0>;
579 compatible = "nvidia,tegra194-p2u";
581 reg-names = "ctl";
583 #phy-cells = <0>;
587 compatible = "nvidia,tegra194-p2u";
589 reg-names = "ctl";
591 #phy-cells = <0>;
595 compatible = "nvidia,tegra194-p2u";
597 reg-names = "ctl";
599 #phy-cells = <0>;
603 compatible = "nvidia,tegra194-p2u";
605 reg-names = "ctl";
607 #phy-cells = <0>;
611 compatible = "nvidia,tegra194-p2u";
613 reg-names = "ctl";
615 #phy-cells = <0>;
619 compatible = "nvidia,tegra194-p2u";
621 reg-names = "ctl";
623 #phy-cells = <0>;
627 compatible = "nvidia,tegra194-p2u";
629 reg-names = "ctl";
631 #phy-cells = <0>;
635 compatible = "nvidia,tegra194-p2u";
637 reg-names = "ctl";
639 #phy-cells = <0>;
643 compatible = "nvidia,tegra194-p2u";
645 reg-names = "ctl";
647 #phy-cells = <0>;
651 compatible = "nvidia,tegra194-p2u";
653 reg-names = "ctl";
655 #phy-cells = <0>;
659 compatible = "nvidia,tegra194-p2u";
661 reg-names = "ctl";
663 #phy-cells = <0>;
667 compatible = "nvidia,tegra194-p2u";
669 reg-names = "ctl";
671 #phy-cells = <0>;
675 compatible = "nvidia,tegra194-p2u";
677 reg-names = "ctl";
679 #phy-cells = <0>;
683 compatible = "nvidia,tegra194-p2u";
685 reg-names = "ctl";
687 #phy-cells = <0>;
691 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
701 interrupt-names = "shared1", "shared2", "shared3", "shared4";
702 #mbox-cells = <2>;
706 compatible = "nvidia,tegra194-i2c";
709 #address-cells = <1>;
710 #size-cells = <0>;
712 clock-names = "div-clk";
714 reset-names = "i2c";
719 compatible = "nvidia,tegra194-i2c";
722 #address-cells = <1>;
723 #size-cells = <0>;
725 clock-names = "div-clk";
727 reset-names = "i2c";
732 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
734 reg-shift = <2>;
737 clock-names = "serial";
739 reset-names = "serial";
744 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
746 reg-shift = <2>;
749 clock-names = "serial";
751 reset-names = "serial";
756 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
758 interrupt-parent = <&pmc>;
761 clock-names = "rtc";
766 compatible = "nvidia,tegra194-gpio-aon";
767 reg-names = "security", "gpio";
774 gpio-controller;
775 #gpio-cells = <2>;
776 interrupt-controller;
777 #interrupt-cells = <2>;
781 compatible = "nvidia,tegra194-pwm",
782 "nvidia,tegra186-pwm";
785 clock-names = "pwm";
787 reset-names = "pwm";
789 #pwm-cells = <2>;
793 compatible = "nvidia,tegra194-pmc";
799 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
801 #interrupt-cells = <2>;
802 interrupt-controller;
806 compatible = "nvidia,tegra194-host1x", "simple-bus";
809 reg-names = "hypervisor", "vm";
813 clock-names = "host1x";
815 reset-names = "host1x";
817 #address-cells = <1>;
818 #size-cells = <1>;
822 display-hub@15200000 {
823 compatible = "nvidia,tegra194-display", "simple-bus";
832 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
836 clock-names = "disp", "hub";
839 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
841 #address-cells = <1>;
842 #size-cells = <1>;
847 compatible = "nvidia,tegra194-dc";
851 clock-names = "dc";
853 reset-names = "dc";
855 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
862 compatible = "nvidia,tegra194-dc";
866 clock-names = "dc";
868 reset-names = "dc";
870 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
877 compatible = "nvidia,tegra194-dc";
881 clock-names = "dc";
883 reset-names = "dc";
885 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
892 compatible = "nvidia,tegra194-dc";
896 clock-names = "dc";
898 reset-names = "dc";
900 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
908 compatible = "nvidia,tegra194-vic";
912 clock-names = "vic";
914 reset-names = "vic";
916 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
920 compatible = "nvidia,tegra194-dpaux";
925 clock-names = "dpaux", "parent";
927 reset-names = "dpaux";
930 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
932 state_dpaux0_aux: pinmux-aux {
933 groups = "dpaux-io";
937 state_dpaux0_i2c: pinmux-i2c {
938 groups = "dpaux-io";
942 state_dpaux0_off: pinmux-off {
943 groups = "dpaux-io";
947 i2c-bus {
948 #address-cells = <1>;
949 #size-cells = <0>;
954 compatible = "nvidia,tegra194-dpaux";
959 clock-names = "dpaux", "parent";
961 reset-names = "dpaux";
964 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
966 state_dpaux1_aux: pinmux-aux {
967 groups = "dpaux-io";
971 state_dpaux1_i2c: pinmux-i2c {
972 groups = "dpaux-io";
976 state_dpaux1_off: pinmux-off {
977 groups = "dpaux-io";
981 i2c-bus {
982 #address-cells = <1>;
983 #size-cells = <0>;
988 compatible = "nvidia,tegra194-dpaux";
993 clock-names = "dpaux", "parent";
995 reset-names = "dpaux";
998 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1000 state_dpaux2_aux: pinmux-aux {
1001 groups = "dpaux-io";
1005 state_dpaux2_i2c: pinmux-i2c {
1006 groups = "dpaux-io";
1010 state_dpaux2_off: pinmux-off {
1011 groups = "dpaux-io";
1015 i2c-bus {
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1022 compatible = "nvidia,tegra194-dpaux";
1027 clock-names = "dpaux", "parent";
1029 reset-names = "dpaux";
1032 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1034 state_dpaux3_aux: pinmux-aux {
1035 groups = "dpaux-io";
1039 state_dpaux3_i2c: pinmux-i2c {
1040 groups = "dpaux-io";
1044 state_dpaux3_off: pinmux-off {
1045 groups = "dpaux-io";
1049 i2c-bus {
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1056 compatible = "nvidia,tegra194-sor";
1065 clock-names = "sor", "out", "parent", "dp", "safe",
1068 reset-names = "sor";
1069 pinctrl-0 = <&state_dpaux0_aux>;
1070 pinctrl-1 = <&state_dpaux0_i2c>;
1071 pinctrl-2 = <&state_dpaux0_off>;
1072 pinctrl-names = "aux", "i2c", "off";
1075 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1080 compatible = "nvidia,tegra194-sor";
1089 clock-names = "sor", "out", "parent", "dp", "safe",
1092 reset-names = "sor";
1093 pinctrl-0 = <&state_dpaux1_aux>;
1094 pinctrl-1 = <&state_dpaux1_i2c>;
1095 pinctrl-2 = <&state_dpaux1_off>;
1096 pinctrl-names = "aux", "i2c", "off";
1099 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1104 compatible = "nvidia,tegra194-sor";
1113 clock-names = "sor", "out", "parent", "dp", "safe",
1116 reset-names = "sor";
1117 pinctrl-0 = <&state_dpaux2_aux>;
1118 pinctrl-1 = <&state_dpaux2_i2c>;
1119 pinctrl-2 = <&state_dpaux2_off>;
1120 pinctrl-names = "aux", "i2c", "off";
1123 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1128 compatible = "nvidia,tegra194-sor";
1137 clock-names = "sor", "out", "parent", "dp", "safe",
1140 reset-names = "sor";
1141 pinctrl-0 = <&state_dpaux3_aux>;
1142 pinctrl-1 = <&state_dpaux3_i2c>;
1143 pinctrl-2 = <&state_dpaux3_off>;
1144 pinctrl-names = "aux", "i2c", "off";
1147 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1154 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1155 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1160 reg-names = "appl", "config", "atu_dma", "dbi";
1164 #address-cells = <3>;
1165 #size-cells = <2>;
1167 num-lanes = <1>;
1168 num-viewport = <8>;
1169 linux,pci-domain = <1>;
1172 clock-names = "core";
1176 reset-names = "apb", "core";
1180 interrupt-names = "intr", "msi";
1182 #interrupt-cells = <1>;
1183 interrupt-map-mask = <0 0 0 0>;
1184 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1188 supports-clkreq;
1189 nvidia,aspm-cmrt-us = <60>;
1190 nvidia,aspm-pwr-on-t-us = <20>;
1191 nvidia,aspm-l0s-entrance-latency-us = <3>;
1193 bus-range = <0x0 0xff>;
1196 … 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1200 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1201 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1206 reg-names = "appl", "config", "atu_dma", "dbi";
1210 #address-cells = <3>;
1211 #size-cells = <2>;
1213 num-lanes = <1>;
1214 num-viewport = <8>;
1215 linux,pci-domain = <2>;
1218 clock-names = "core";
1222 reset-names = "apb", "core";
1226 interrupt-names = "intr", "msi";
1228 #interrupt-cells = <1>;
1229 interrupt-map-mask = <0 0 0 0>;
1230 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1234 supports-clkreq;
1235 nvidia,aspm-cmrt-us = <60>;
1236 nvidia,aspm-pwr-on-t-us = <20>;
1237 nvidia,aspm-l0s-entrance-latency-us = <3>;
1239 bus-range = <0x0 0xff>;
1242 … 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1246 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1247 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1252 reg-names = "appl", "config", "atu_dma", "dbi";
1256 #address-cells = <3>;
1257 #size-cells = <2>;
1259 num-lanes = <1>;
1260 num-viewport = <8>;
1261 linux,pci-domain = <3>;
1264 clock-names = "core";
1268 reset-names = "apb", "core";
1272 interrupt-names = "intr", "msi";
1274 #interrupt-cells = <1>;
1275 interrupt-map-mask = <0 0 0 0>;
1276 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1280 supports-clkreq;
1281 nvidia,aspm-cmrt-us = <60>;
1282 nvidia,aspm-pwr-on-t-us = <20>;
1283 nvidia,aspm-l0s-entrance-latency-us = <3>;
1285 bus-range = <0x0 0xff>;
1288 … 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1292 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1293 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1298 reg-names = "appl", "config", "atu_dma", "dbi";
1302 #address-cells = <3>;
1303 #size-cells = <2>;
1305 num-lanes = <4>;
1306 num-viewport = <8>;
1307 linux,pci-domain = <4>;
1310 clock-names = "core";
1314 reset-names = "apb", "core";
1318 interrupt-names = "intr", "msi";
1320 #interrupt-cells = <1>;
1321 interrupt-map-mask = <0 0 0 0>;
1322 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1326 supports-clkreq;
1327 nvidia,aspm-cmrt-us = <60>;
1328 nvidia,aspm-pwr-on-t-us = <20>;
1329 nvidia,aspm-l0s-entrance-latency-us = <3>;
1331 bus-range = <0x0 0xff>;
1334 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1338 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1339 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1344 reg-names = "appl", "config", "atu_dma", "dbi";
1348 #address-cells = <3>;
1349 #size-cells = <2>;
1351 num-lanes = <8>;
1352 num-viewport = <8>;
1353 linux,pci-domain = <0>;
1356 clock-names = "core";
1360 reset-names = "apb", "core";
1364 interrupt-names = "intr", "msi";
1366 #interrupt-cells = <1>;
1367 interrupt-map-mask = <0 0 0 0>;
1368 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1372 supports-clkreq;
1373 nvidia,aspm-cmrt-us = <60>;
1374 nvidia,aspm-pwr-on-t-us = <20>;
1375 nvidia,aspm-l0s-entrance-latency-us = <3>;
1377 bus-range = <0x0 0xff>;
1380 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1384 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1385 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1390 reg-names = "appl", "config", "atu_dma", "dbi";
1394 #address-cells = <3>;
1395 #size-cells = <2>;
1397 num-lanes = <8>;
1398 num-viewport = <8>;
1399 linux,pci-domain = <5>;
1401 pinctrl-names = "default";
1402 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
1406 clock-names = "core", "core_m";
1410 reset-names = "apb", "core";
1414 interrupt-names = "intr", "msi";
1418 #interrupt-cells = <1>;
1419 interrupt-map-mask = <0 0 0 0>;
1420 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1422 supports-clkreq;
1423 nvidia,aspm-cmrt-us = <60>;
1424 nvidia,aspm-pwr-on-t-us = <20>;
1425 nvidia,aspm-l0s-entrance-latency-us = <3>;
1427 bus-range = <0x0 0xff>;
1430 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1434 compatible = "nvidia,tegra194-sysram", "mmio-sram";
1436 #address-cells = <1>;
1437 #size-cells = <1>;
1441 compatible = "nvidia,tegra194-bpmp-shmem";
1443 label = "cpu-bpmp-tx";
1448 compatible = "nvidia,tegra194-bpmp-shmem";
1450 label = "cpu-bpmp-rx";
1456 compatible = "nvidia,tegra186-bpmp";
1460 #clock-cells = <1>;
1461 #reset-cells = <1>;
1462 #power-domain-cells = <1>;
1465 compatible = "nvidia,tegra186-bpmp-i2c";
1466 nvidia,bpmp-bus-id = <5>;
1467 #address-cells = <1>;
1468 #size-cells = <0>;
1472 compatible = "nvidia,tegra186-bpmp-thermal";
1473 #thermal-sensor-cells = <1>;
1478 #address-cells = <1>;
1479 #size-cells = <0>;
1482 compatible = "nvidia,tegra194-carmel";
1485 enable-method = "psci";
1489 compatible = "nvidia,tegra194-carmel";
1492 enable-method = "psci";
1496 compatible = "nvidia,tegra194-carmel";
1499 enable-method = "psci";
1503 compatible = "nvidia,tegra194-carmel";
1506 enable-method = "psci";
1510 compatible = "nvidia,tegra194-carmel";
1513 enable-method = "psci";
1517 compatible = "nvidia,tegra194-carmel";
1520 enable-method = "psci";
1524 compatible = "nvidia,tegra194-carmel";
1527 enable-method = "psci";
1531 compatible = "nvidia,tegra194-carmel";
1534 enable-method = "psci";
1539 compatible = "arm,psci-1.0";
1545 compatible = "nvidia,tegra194-tcu";
1548 mbox-names = "rx", "tx";
1551 thermal-zones {
1553 thermal-sensors = <&{/bpmp/thermal}
1559 thermal-sensors = <&{/bpmp/thermal}
1565 thermal-sensors = <&{/bpmp/thermal}
1571 thermal-sensors = <&{/bpmp/thermal}
1577 thermal-sensors = <&{/bpmp/thermal}
1583 thermal-sensors = <&{/bpmp/thermal}
1590 compatible = "arm,armv8-timer";
1599 interrupt-parent = <&gic>;
1600 always-on;