Lines Matching +full:psci +full:- +full:0
14 #include <dt-bindings/clock/mt6797-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
21 interrupt-parent = <&sysirq>;
22 #address-cells = <2>;
23 #size-cells = <2>;
25 psci {
26 compatible = "arm,psci-0.2";
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
36 compatible = "arm,cortex-a53";
37 enable-method = "psci";
38 reg = <0x000>;
43 compatible = "arm,cortex-a53";
44 enable-method = "psci";
45 reg = <0x001>;
50 compatible = "arm,cortex-a53";
51 enable-method = "psci";
52 reg = <0x002>;
57 compatible = "arm,cortex-a53";
58 enable-method = "psci";
59 reg = <0x003>;
64 compatible = "arm,cortex-a53";
65 enable-method = "psci";
66 reg = <0x100>;
71 compatible = "arm,cortex-a53";
72 enable-method = "psci";
73 reg = <0x101>;
78 compatible = "arm,cortex-a53";
79 enable-method = "psci";
80 reg = <0x102>;
85 compatible = "arm,cortex-a53";
86 enable-method = "psci";
87 reg = <0x103>;
92 compatible = "arm,cortex-a72";
93 enable-method = "psci";
94 reg = <0x200>;
99 compatible = "arm,cortex-a72";
100 enable-method = "psci";
101 reg = <0x201>;
105 clk26m: oscillator@0 {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <26000000>;
109 clock-output-names = "clk26m";
113 compatible = "arm,armv8-timer";
114 interrupt-parent = <&gic>;
122 compatible = "mediatek,mt6797-topckgen";
123 reg = <0 0x10000000 0 0x1000>;
124 #clock-cells = <1>;
128 compatible = "mediatek,mt6797-infracfg", "syscon";
129 reg = <0 0x10001000 0 0x1000>;
130 #clock-cells = <1>;
134 compatible = "mediatek,mt6797-pinctrl";
135 reg = <0 0x10005000 0 0x1000>,
136 <0 0x10002000 0 0x400>,
137 <0 0x10002400 0 0x400>,
138 <0 0x10002800 0 0x400>,
139 <0 0x10002C00 0 0x400>;
140 reg-names = "gpio", "iocfgl", "iocfgb",
142 gpio-controller;
143 #gpio-cells = <2>;
161 compatible = "mediatek,mt6797-scpsys";
162 #power-domain-cells = <1>;
163 reg = <0 0x10006000 0 0x1000>;
167 clock-names = "mfg", "mm", "vdec";
172 compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
173 reg = <0 0x10007000 0 0x100>;
177 compatible = "mediatek,mt6797-apmixedsys";
178 reg = <0 0x1000c000 0 0x1000>;
179 #clock-cells = <1>;
182 sysirq: intpol-controller@10200620 {
183 compatible = "mediatek,mt6797-sysirq",
184 "mediatek,mt6577-sysirq";
185 interrupt-controller;
186 #interrupt-cells = <3>;
187 interrupt-parent = <&gic>;
188 reg = <0 0x10220620 0 0x20>,
189 <0 0x10220690 0 0x10>;
193 compatible = "mediatek,mt6797-uart",
194 "mediatek,mt6577-uart";
195 reg = <0 0x11002000 0 0x400>;
199 clock-names = "baud", "bus";
204 compatible = "mediatek,mt6797-uart",
205 "mediatek,mt6577-uart";
206 reg = <0 0x11003000 0 0x400>;
210 clock-names = "baud", "bus";
215 compatible = "mediatek,mt6797-uart",
216 "mediatek,mt6577-uart";
217 reg = <0 0x11004000 0 0x400>;
221 clock-names = "baud", "bus";
226 compatible = "mediatek,mt6797-uart",
227 "mediatek,mt6577-uart";
228 reg = <0 0x11005000 0 0x400>;
232 clock-names = "baud", "bus";
237 compatible = "mediatek,mt6797-mmsys", "syscon";
238 reg = <0 0x14000000 0 0x1000>;
239 #clock-cells = <1>;
243 compatible = "mediatek,mt6797-imgsys", "syscon";
244 reg = <0 0x15000000 0 0x1000>;
245 #clock-cells = <1>;
249 compatible = "mediatek,mt6797-vdecsys", "syscon";
250 reg = <0 0x16000000 0 0x10000>;
251 #clock-cells = <1>;
255 compatible = "mediatek,mt6797-vencsys", "syscon";
256 reg = <0 0x17000000 0 0x1000>;
257 #clock-cells = <1>;
260 gic: interrupt-controller@19000000 {
261 compatible = "arm,gic-v3";
262 #interrupt-cells = <3>;
263 interrupt-parent = <&gic>;
265 interrupt-controller;
266 reg = <0 0x19000000 0 0x10000>, /* GICD */
267 <0 0x19200000 0 0x200000>, /* GICR */
268 <0 0x10240000 0 0x2000>; /* GICC */