Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "operating-points-v2";
24 opp-shared;
26 opp-hz = /bits/ 64 <598000000>;
27 opp-microvolt = <1000000>;
30 opp-hz = /bits/ 64 <702000000>;
31 opp-microvolt = <1000000>;
34 opp-hz = /bits/ 64 <793000000>;
35 opp-microvolt = <1000000>;
40 compatible = "operating-points-v2";
41 opp-shared;
43 opp-hz = /bits/ 64 <598000000>;
44 opp-microvolt = <1000000>;
47 opp-hz = /bits/ 64 <702000000>;
48 opp-microvolt = <1000000>;
51 opp-hz = /bits/ 64 <793000000>;
52 opp-microvolt = <1000000>;
55 opp-hz = /bits/ 64 <897000000>;
56 opp-microvolt = <1000000>;
59 opp-hz = /bits/ 64 <1001000000>;
60 opp-microvolt = <1000000>;
65 #address-cells = <1>;
66 #size-cells = <0>;
68 cpu-map {
87 compatible = "arm,cortex-a35";
91 clock-names = "cpu", "intermediate";
92 proc-supply = <&cpus_fixed_vproc0>;
93 operating-points-v2 = <&cluster0_opp>;
94 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
99 compatible = "arm,cortex-a35";
101 enable-method = "psci";
104 clock-names = "cpu", "intermediate";
105 proc-supply = <&cpus_fixed_vproc0>;
106 operating-points-v2 = <&cluster0_opp>;
107 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
112 compatible = "arm,cortex-a72";
114 enable-method = "psci";
117 clock-names = "cpu", "intermediate";
118 proc-supply = <&cpus_fixed_vproc1>;
119 operating-points-v2 = <&cluster1_opp>;
120 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
123 idle-states {
124 entry-method = "psci";
126 CPU_SLEEP_0: cpu-sleep-0 {
127 compatible = "arm,idle-state";
128 local-timer-stop;
129 entry-latency-us = <100>;
130 exit-latency-us = <80>;
131 min-residency-us = <2000>;
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
136 compatible = "arm,idle-state";
137 local-timer-stop;
138 entry-latency-us = <350>;
139 exit-latency-us = <80>;
140 min-residency-us = <3000>;
141 arm,psci-suspend-param = <0x1010000>;
146 psci {
147 compatible = "arm,psci-0.2";
152 compatible = "fixed-clock";
153 clock-frequency = <26000000>;
154 #clock-cells = <0>;
158 compatible = "fixed-clock";
159 clock-frequency = <26000000>;
160 #clock-cells = <0>;
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <26000000>;
167 clock-output-names = "clk26m";
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <32768>;
174 clock-output-names = "clk32k";
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <50000000>;
181 clock-output-names = "clkfpc";
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <6500000>;
188 clock-output-names = "clkaud_ext_i_0";
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <196608000>;
195 clock-output-names = "clkaud_ext_i_1";
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <180633600>;
202 clock-output-names = "clkaud_ext_i_2";
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <30000000>;
209 clock-output-names = "clki2si0_mck_i";
213 compatible = "fixed-clock";
214 #clock-cells = <0>;
215 clock-frequency = <30000000>;
216 clock-output-names = "clki2si1_mck_i";
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <30000000>;
223 clock-output-names = "clki2si2_mck_i";
227 compatible = "fixed-clock";
228 #clock-cells = <0>;
229 clock-frequency = <30000000>;
230 clock-output-names = "clktdmin_mclk_i";
234 compatible = "arm,armv8-timer";
235 interrupt-parent = <&gic>;
247 compatible = "mediatek,mt2712-topckgen", "syscon";
249 #clock-cells = <1>;
253 compatible = "mediatek,mt2712-infracfg", "syscon";
255 #clock-cells = <1>;
259 compatible = "mediatek,mt2712-pericfg", "syscon";
261 #clock-cells = <1>;
265 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
270 compatible = "mediatek,mt2712-pinctrl";
272 mediatek,pctl-regmap = <&syscfg_pctl_a>;
273 pins-are-numbered;
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
282 compatible = "mediatek,mt2712-scpsys", "syscon";
283 #power-domain-cells = <1>;
291 clock-names = "mm", "mfg", "venc",
297 compatible = "mediatek,mt2712-uart",
298 "mediatek,mt6577-uart";
302 clock-names = "baud", "bus";
307 compatible = "mediatek,mt2712-spi-slave";
311 clock-names = "spi";
312 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
313 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
318 compatible = "mediatek,mt2712-m4u";
322 clock-names = "bclk";
325 #iommu-cells = <1>;
329 compatible = "mediatek,mt2712-apmixedsys", "syscon";
331 #clock-cells = <1>;
335 compatible = "mediatek,mt2712-m4u";
339 clock-names = "bclk";
341 #iommu-cells = <1>;
345 compatible = "mediatek,mt2712-mcucfg", "syscon";
347 #clock-cells = <1>;
350 sysirq: interrupt-controller@10220a80 {
351 compatible = "mediatek,mt2712-sysirq",
352 "mediatek,mt6577-sysirq";
353 interrupt-controller;
354 #interrupt-cells = <3>;
355 interrupt-parent = <&gic>;
359 gic: interrupt-controller@10510000 {
360 compatible = "arm,gic-400";
361 #interrupt-cells = <3>;
362 interrupt-parent = <&gic>;
363 interrupt-controller;
373 compatible = "mediatek,mt2712-auxadc";
376 clock-names = "main";
377 #io-channel-cells = <1>;
382 compatible = "mediatek,mt2712-uart",
383 "mediatek,mt6577-uart";
387 clock-names = "baud", "bus";
392 compatible = "mediatek,mt2712-uart",
393 "mediatek,mt6577-uart";
397 clock-names = "baud", "bus";
402 compatible = "mediatek,mt2712-uart",
403 "mediatek,mt6577-uart";
407 clock-names = "baud", "bus";
412 compatible = "mediatek,mt2712-uart",
413 "mediatek,mt6577-uart";
417 clock-names = "baud", "bus";
422 compatible = "mediatek,mt2712-pwm";
424 #pwm-cells = <2>;
436 clock-names = "top",
450 compatible = "mediatek,mt2712-i2c";
454 clock-div = <4>;
457 clock-names = "main",
459 #address-cells = <1>;
460 #size-cells = <0>;
465 compatible = "mediatek,mt2712-i2c";
469 clock-div = <4>;
472 clock-names = "main",
474 #address-cells = <1>;
475 #size-cells = <0>;
480 compatible = "mediatek,mt2712-i2c";
484 clock-div = <4>;
487 clock-names = "main",
489 #address-cells = <1>;
490 #size-cells = <0>;
495 compatible = "mediatek,mt2712-spi";
496 #address-cells = <1>;
497 #size-cells = <0>;
503 clock-names = "parent-clk", "sel-clk", "spi-clk";
508 compatible = "mediatek,mt2712-nfc";
512 clock-names = "nfi_clk", "pad_clk";
513 ecc-engine = <&bch>;
514 #address-cells = <1>;
515 #size-cells = <0>;
520 compatible = "mediatek,mt2712-ecc";
524 clock-names = "nfiecc_clk";
529 compatible = "mediatek,mt2712-i2c";
533 clock-div = <4>;
536 clock-names = "main",
538 #address-cells = <1>;
539 #size-cells = <0>;
544 compatible = "mediatek,mt2712-i2c";
548 clock-div = <4>;
551 clock-names = "main",
553 #address-cells = <1>;
554 #size-cells = <0>;
559 compatible = "mediatek,mt2712-i2c";
563 clock-div = <4>;
566 clock-names = "main",
568 #address-cells = <1>;
569 #size-cells = <0>;
574 compatible = "mediatek,mt2712-spi";
575 #address-cells = <1>;
576 #size-cells = <0>;
582 clock-names = "parent-clk", "sel-clk", "spi-clk";
587 compatible = "mediatek,mt2712-spi";
588 #address-cells = <1>;
589 #size-cells = <0>;
595 clock-names = "parent-clk", "sel-clk", "spi-clk";
600 compatible = "mediatek,mt2712-spi";
601 #address-cells = <1>;
602 #size-cells = <0>;
608 clock-names = "parent-clk", "sel-clk", "spi-clk";
613 compatible = "mediatek,mt2712-spi";
614 #address-cells = <1>;
615 #size-cells = <0>;
621 clock-names = "parent-clk", "sel-clk", "spi-clk";
626 compatible = "mediatek,mt2712-uart",
627 "mediatek,mt6577-uart";
631 clock-names = "baud", "bus";
636 compatible = "mediatek,mt2712-mmc";
643 clock-names = "source", "hclk", "bus_clk", "source_cg";
648 compatible = "mediatek,mt2712-mmc";
654 clock-names = "source", "hclk", "source_cg";
659 compatible = "mediatek,mt2712-mmc";
665 clock-names = "source", "hclk", "source_cg";
670 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
673 reg-names = "mac", "ippc";
677 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
679 clock-names = "sys_ck";
680 mediatek,syscon-wakeup = <&pericfg 0x510 2>;
681 #address-cells = <2>;
682 #size-cells = <2>;
687 compatible = "mediatek,mt2712-xhci",
688 "mediatek,mtk-xhci";
690 reg-names = "mac";
692 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
694 clock-names = "sys_ck", "ref_ck";
699 u3phy0: usb-phy@11290000 {
700 compatible = "mediatek,mt2712-u3phy";
701 #address-cells = <2>;
702 #size-cells = <2>;
706 u2port0: usb-phy@11290000 {
709 clock-names = "ref";
710 #phy-cells = <1>;
714 u2port1: usb-phy@11298000 {
717 clock-names = "ref";
718 #phy-cells = <1>;
722 u3port0: usb-phy@11298700 {
725 clock-names = "ref";
726 #phy-cells = <1>;
732 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
735 reg-names = "mac", "ippc";
740 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
742 clock-names = "sys_ck";
743 mediatek,syscon-wakeup = <&pericfg 0x514 2>;
744 #address-cells = <2>;
745 #size-cells = <2>;
750 compatible = "mediatek,mt2712-xhci",
751 "mediatek,mtk-xhci";
753 reg-names = "mac";
755 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
757 clock-names = "sys_ck", "ref_ck";
762 u3phy1: usb-phy@112e0000 {
763 compatible = "mediatek,mt2712-u3phy";
764 #address-cells = <2>;
765 #size-cells = <2>;
769 u2port2: usb-phy@112e0000 {
772 clock-names = "ref";
773 #phy-cells = <1>;
777 u2port3: usb-phy@112e8000 {
780 clock-names = "ref";
781 #phy-cells = <1>;
785 u3port1: usb-phy@112e8700 {
788 clock-names = "ref";
789 #phy-cells = <1>;
795 compatible = "mediatek,mt2712-pcie";
799 reg-names = "port0", "port1";
800 #address-cells = <3>;
801 #size-cells = <2>;
808 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
810 phy-names = "pcie-phy0", "pcie-phy1";
811 bus-range = <0x00 0xff>;
818 #address-cells = <3>;
819 #size-cells = <2>;
820 #interrupt-cells = <1>;
822 interrupt-map-mask = <0 0 0 7>;
823 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
827 pcie_intc0: interrupt-controller {
828 interrupt-controller;
829 #address-cells = <0>;
830 #interrupt-cells = <1>;
838 #address-cells = <3>;
839 #size-cells = <2>;
840 #interrupt-cells = <1>;
842 interrupt-map-mask = <0 0 0 7>;
843 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
847 pcie_intc1: interrupt-controller {
848 interrupt-controller;
849 #address-cells = <0>;
850 #interrupt-cells = <1>;
856 compatible = "mediatek,mt2712-mfgcfg", "syscon";
858 #clock-cells = <1>;
862 compatible = "mediatek,mt2712-mmsys", "syscon";
864 #clock-cells = <1>;
868 compatible = "mediatek,mt2712-smi-larb";
871 mediatek,larb-id = <0>;
872 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
875 clock-names = "apb", "smi";
879 compatible = "mediatek,mt2712-smi-common";
881 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
884 clock-names = "apb", "smi";
888 compatible = "mediatek,mt2712-smi-larb";
891 mediatek,larb-id = <4>;
892 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
895 clock-names = "apb", "smi";
899 compatible = "mediatek,mt2712-smi-larb";
902 mediatek,larb-id = <5>;
903 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
906 clock-names = "apb", "smi";
910 compatible = "mediatek,mt2712-smi-common";
912 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
915 clock-names = "apb", "smi";
919 compatible = "mediatek,mt2712-smi-larb";
922 mediatek,larb-id = <7>;
923 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
926 clock-names = "apb", "smi";
930 compatible = "mediatek,mt2712-imgsys", "syscon";
932 #clock-cells = <1>;
936 compatible = "mediatek,mt2712-smi-larb";
939 mediatek,larb-id = <2>;
940 power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
943 clock-names = "apb", "smi";
947 compatible = "mediatek,mt2712-bdpsys", "syscon";
949 #clock-cells = <1>;
953 compatible = "mediatek,mt2712-vdecsys", "syscon";
955 #clock-cells = <1>;
959 compatible = "mediatek,mt2712-smi-larb";
962 mediatek,larb-id = <1>;
963 power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
966 clock-names = "apb", "smi";
970 compatible = "mediatek,mt2712-vencsys", "syscon";
972 #clock-cells = <1>;
976 compatible = "mediatek,mt2712-smi-larb";
979 mediatek,larb-id = <3>;
980 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
983 clock-names = "apb", "smi";
987 compatible = "mediatek,mt2712-smi-larb";
990 mediatek,larb-id = <6>;
991 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
994 clock-names = "apb", "smi";
998 compatible = "mediatek,mt2712-jpgdecsys", "syscon";
1000 #clock-cells = <1>;