Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 psci {
21 compatible = "arm,psci-0.2";
26 #address-cells = <2>;
27 #size-cells = <0>;
29 cpu-map {
60 idle-states {
61 entry-method = "psci";
63 CPU_SLEEP: cpu-sleep {
64 compatible = "arm,idle-state";
65 local-timer-stop;
66 arm,psci-suspend-param = <0x0010000>;
67 entry-latency-us = <700>;
68 exit-latency-us = <250>;
69 min-residency-us = <1000>;
72 CLUSTER_SLEEP: cluster-sleep {
73 compatible = "arm,idle-state";
74 local-timer-stop;
75 arm,psci-suspend-param = <0x1010000>;
76 entry-latency-us = <1000>;
77 exit-latency-us = <700>;
78 min-residency-us = <2700>;
79 wakeup-latency-us = <1500>;
84 compatible = "arm,cortex-a53";
87 enable-method = "psci";
88 next-level-cache = <&CLUSTER0_L2>;
90 operating-points-v2 = <&cpu_opp_table>;
91 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
92 #cooling-cells = <2>; /* min followed by max */
93 dynamic-power-coefficient = <311>;
97 compatible = "arm,cortex-a53";
100 enable-method = "psci";
101 next-level-cache = <&CLUSTER0_L2>;
103 operating-points-v2 = <&cpu_opp_table>;
104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
105 #cooling-cells = <2>; /* min followed by max */
106 dynamic-power-coefficient = <311>;
110 compatible = "arm,cortex-a53";
113 enable-method = "psci";
114 next-level-cache = <&CLUSTER0_L2>;
116 operating-points-v2 = <&cpu_opp_table>;
117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coefficient = <311>;
123 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 next-level-cache = <&CLUSTER0_L2>;
129 operating-points-v2 = <&cpu_opp_table>;
130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 #cooling-cells = <2>; /* min followed by max */
132 dynamic-power-coefficient = <311>;
136 compatible = "arm,cortex-a53";
139 enable-method = "psci";
140 next-level-cache = <&CLUSTER1_L2>;
142 operating-points-v2 = <&cpu_opp_table>;
143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 #cooling-cells = <2>; /* min followed by max */
145 dynamic-power-coefficient = <311>;
149 compatible = "arm,cortex-a53";
152 enable-method = "psci";
153 next-level-cache = <&CLUSTER1_L2>;
155 operating-points-v2 = <&cpu_opp_table>;
156 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
157 #cooling-cells = <2>; /* min followed by max */
158 dynamic-power-coefficient = <311>;
162 compatible = "arm,cortex-a53";
165 enable-method = "psci";
166 next-level-cache = <&CLUSTER1_L2>;
168 operating-points-v2 = <&cpu_opp_table>;
169 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
170 #cooling-cells = <2>; /* min followed by max */
171 dynamic-power-coefficient = <311>;
175 compatible = "arm,cortex-a53";
178 enable-method = "psci";
179 next-level-cache = <&CLUSTER1_L2>;
181 operating-points-v2 = <&cpu_opp_table>;
182 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
183 #cooling-cells = <2>; /* min followed by max */
184 dynamic-power-coefficient = <311>;
187 CLUSTER0_L2: l2-cache0 {
191 CLUSTER1_L2: l2-cache1 {
197 compatible = "operating-points-v2";
198 opp-shared;
201 opp-hz = /bits/ 64 <208000000>;
202 opp-microvolt = <1040000>;
203 clock-latency-ns = <500000>;
206 opp-hz = /bits/ 64 <432000000>;
207 opp-microvolt = <1040000>;
208 clock-latency-ns = <500000>;
211 opp-hz = /bits/ 64 <729000000>;
212 opp-microvolt = <1090000>;
213 clock-latency-ns = <500000>;
216 opp-hz = /bits/ 64 <960000000>;
217 opp-microvolt = <1180000>;
218 clock-latency-ns = <500000>;
221 opp-hz = /bits/ 64 <1200000000>;
222 opp-microvolt = <1330000>;
223 clock-latency-ns = <500000>;
227 gic: interrupt-controller@f6801000 {
228 compatible = "arm,gic-400";
233 #address-cells = <0>;
234 #interrupt-cells = <3>;
235 interrupt-controller;
240 compatible = "arm,armv8-timer";
241 interrupt-parent = <&gic>;
249 compatible = "simple-bus";
250 #address-cells = <2>;
251 #size-cells = <2>;
255 compatible = "hisilicon,hi6220-sramctrl", "syscon";
260 compatible = "hisilicon,hi6220-aoctrl", "syscon";
262 #clock-cells = <1>;
266 compatible = "hisilicon,hi6220-sysctrl", "syscon";
268 #clock-cells = <1>;
269 #reset-cells = <1>;
273 compatible = "hisilicon,hi6220-mediactrl", "syscon";
275 #clock-cells = <1>;
276 #reset-cells = <1>;
280 compatible = "hisilicon,hi6220-pmctrl", "syscon";
282 #clock-cells = <1>;
286 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
288 #clock-cells = <1>;
297 compatible = "hisilicon,hi6220-stub-clk";
298 hisilicon,hi6220-clk-sram = <&sram>;
299 #clock-cells = <1>;
300 mbox-names = "mbox-tx";
310 clock-names = "uartclk", "apb_pclk";
319 clock-names = "uartclk", "apb_pclk";
320 pinctrl-names = "default";
321 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
323 dma-names = "rx", "tx";
333 clock-names = "uartclk", "apb_pclk";
334 pinctrl-names = "default";
335 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
345 clock-names = "uartclk", "apb_pclk";
346 pinctrl-names = "default";
347 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
357 clock-names = "uartclk", "apb_pclk";
358 pinctrl-names = "default";
359 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
364 compatible = "hisilicon,k3-dma-1.0";
366 #dma-cells = <1>;
367 dma-channels = <15>;
368 dma-requests = <32>;
371 dma-no-cci;
372 dma-type = "hi6220_dma";
384 clock-names = "timer1", "timer2", "apb_pclk";
392 clock-names = "apb_pclk";
400 clock-names = "apb_pclk";
404 compatible = "pinctrl-single";
406 #address-cells = <1>;
407 #size-cells = <1>;
408 #pinctrl-cells = <1>;
409 #gpio-range-cells = <3>;
410 pinctrl-single,register-width = <32>;
411 pinctrl-single,function-mask = <7>;
412 pinctrl-single,gpio-range = <
437 range: gpio-range {
438 #pinctrl-single,gpio-range-cells = <3>;
443 compatible = "pinconf-single";
445 #address-cells = <1>;
446 #size-cells = <1>;
447 #pinctrl-cells = <1>;
448 pinctrl-single,register-width = <32>;
452 compatible = "pinconf-single";
454 #address-cells = <1>;
455 #size-cells = <1>;
456 #pinctrl-cells = <1>;
457 pinctrl-single,register-width = <32>;
464 gpio-controller;
465 #gpio-cells = <2>;
466 interrupt-controller;
467 #interrupt-cells = <2>;
469 clock-names = "apb_pclk";
476 gpio-controller;
477 #gpio-cells = <2>;
478 interrupt-controller;
479 #interrupt-cells = <2>;
481 clock-names = "apb_pclk";
488 gpio-controller;
489 #gpio-cells = <2>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
493 clock-names = "apb_pclk";
500 gpio-controller;
501 #gpio-cells = <2>;
502 gpio-ranges = <&pmx0 0 80 8>;
503 interrupt-controller;
504 #interrupt-cells = <2>;
506 clock-names = "apb_pclk";
513 gpio-controller;
514 #gpio-cells = <2>;
515 gpio-ranges = <&pmx0 0 88 8>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
519 clock-names = "apb_pclk";
526 gpio-controller;
527 #gpio-cells = <2>;
528 gpio-ranges = <&pmx0 0 96 8>;
529 interrupt-controller;
530 #interrupt-cells = <2>;
532 clock-names = "apb_pclk";
539 gpio-controller;
540 #gpio-cells = <2>;
541 gpio-ranges = <&pmx0 0 104 8>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
545 clock-names = "apb_pclk";
552 gpio-controller;
553 #gpio-cells = <2>;
554 gpio-ranges = <&pmx0 0 112 8>;
555 interrupt-controller;
556 #interrupt-cells = <2>;
558 clock-names = "apb_pclk";
565 gpio-controller;
566 #gpio-cells = <2>;
567 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
568 interrupt-controller;
569 #interrupt-cells = <2>;
571 clock-names = "apb_pclk";
578 gpio-controller;
579 #gpio-cells = <2>;
580 gpio-ranges = <&pmx0 0 8 8>;
581 interrupt-controller;
582 #interrupt-cells = <2>;
584 clock-names = "apb_pclk";
591 gpio-controller;
592 #gpio-cells = <2>;
593 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
594 interrupt-controller;
595 #interrupt-cells = <2>;
597 clock-names = "apb_pclk";
604 gpio-controller;
605 #gpio-cells = <2>;
606 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
607 interrupt-controller;
608 #interrupt-cells = <2>;
610 clock-names = "apb_pclk";
617 gpio-controller;
618 #gpio-cells = <2>;
619 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
620 interrupt-controller;
621 #interrupt-cells = <2>;
623 clock-names = "apb_pclk";
630 gpio-controller;
631 #gpio-cells = <2>;
632 gpio-ranges = <&pmx0 0 48 8>;
633 interrupt-controller;
634 #interrupt-cells = <2>;
636 clock-names = "apb_pclk";
643 gpio-controller;
644 #gpio-cells = <2>;
645 gpio-ranges = <&pmx0 0 56 8>;
646 interrupt-controller;
647 #interrupt-cells = <2>;
649 clock-names = "apb_pclk";
656 gpio-controller;
657 #gpio-cells = <2>;
658 gpio-ranges = <
663 interrupt-controller;
664 #interrupt-cells = <2>;
666 clock-names = "apb_pclk";
673 gpio-controller;
674 #gpio-cells = <2>;
675 gpio-ranges = <&pmx0 0 127 8>;
676 interrupt-controller;
677 #interrupt-cells = <2>;
679 clock-names = "apb_pclk";
686 gpio-controller;
687 #gpio-cells = <2>;
688 gpio-ranges = <&pmx0 0 135 8>;
689 interrupt-controller;
690 #interrupt-cells = <2>;
692 clock-names = "apb_pclk";
699 gpio-controller;
700 #gpio-cells = <2>;
701 gpio-ranges = <&pmx0 0 143 8>;
702 interrupt-controller;
703 #interrupt-cells = <2>;
705 clock-names = "apb_pclk";
712 gpio-controller;
713 #gpio-cells = <2>;
714 gpio-ranges = <&pmx0 0 151 8>;
715 interrupt-controller;
716 #interrupt-cells = <2>;
718 clock-names = "apb_pclk";
725 bus-id = <0>;
726 enable-dma = <0>;
728 clock-names = "apb_pclk";
729 pinctrl-names = "default";
730 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
731 num-cs = <1>;
732 cs-gpios = <&gpio6 2 0>;
737 compatible = "snps,designware-i2c";
741 i2c-sda-hold-time-ns = <300>;
742 pinctrl-names = "default";
743 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
748 compatible = "snps,designware-i2c";
752 i2c-sda-hold-time-ns = <300>;
753 pinctrl-names = "default";
754 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
759 compatible = "snps,designware-i2c";
763 i2c-sda-hold-time-ns = <300>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
770 compatible = "hisilicon,hi6220-usb-phy";
771 #phy-cells = <0>;
772 phy-supply = <®_5v_hub>;
773 hisilicon,peripheral-syscon = <&sys_ctrl>;
777 compatible = "hisilicon,hi6220-usb";
780 phy-names = "usb2-phy";
782 clock-names = "otg";
784 g-rx-fifo-size = <512>;
785 g-np-tx-fifo-size = <128>;
786 g-tx-fifo-size = <128 128 128 128 128 128 128 128
792 compatible = "hisilicon,hi6220-mbox";
796 #mbox-cells = <3>;
800 compatible = "hisilicon,hi6220-dw-mshc";
804 clock-names = "ciu", "biu";
806 reset-names = "reset";
807 pinctrl-names = "default";
808 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
813 compatible = "hisilicon,hi6220-dw-mshc";
814 hisilicon,peripheral-syscon = <&ao_ctrl>;
817 #address-cells = <0x1>;
818 #size-cells = <0x0>;
820 clock-names = "ciu", "biu";
822 reset-names = "reset";
823 pinctrl-names = "default", "idle";
824 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
825 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
829 compatible = "hisilicon,hi6220-dw-mshc";
833 clock-names = "ciu", "biu";
835 reset-names = "reset";
836 pinctrl-names = "default", "idle";
837 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
838 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
842 compatible = "arm,sp805-wdt", "arm,primecell";
846 clock-names = "apb_pclk";
854 clock-names = "thermal_clk";
855 #thermal-sensor-cells = <1>;
859 compatible = "hisilicon,hi6210-i2s";
861 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
864 clock-names = "dacodec", "i2s-base";
866 dma-names = "rx", "tx";
867 hisilicon,sysctrl-syscon = <&sys_ctrl>;
868 #sound-dai-cells = <1>;
871 thermal-zones {
874 polling-delay = <1000>;
875 polling-delay-passive = <100>;
876 sustainable-power = <3326>;
879 thermal-sensors = <&tsensor 2>;
882 threshold: trip-point@0 {
888 target: trip-point@1 {
895 cooling-maps {
898 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
912 compatible = "hisilicon,hi6220-ade";
914 reg-names = "ade_base";
915 hisilicon,noc-syscon = <&medianoc_ade>;
923 clock-names = "clk_ade_core",
927 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
929 assigned-clock-rates = <360000000>, <288000000>;
930 dma-coherent;
935 remote-endpoint = <&dsi_in>;
941 compatible = "hisilicon,hi6220-dsi";
944 clock-names = "pclk";
948 #address-cells = <1>;
949 #size-cells = <0>;
955 remote-endpoint = <&ade_out>;
962 compatible = "arm,coresight-cpu-debug","arm,primecell";
965 clock-names = "apb_pclk";
970 compatible = "arm,coresight-cpu-debug","arm,primecell";
973 clock-names = "apb_pclk";
978 compatible = "arm,coresight-cpu-debug","arm,primecell";
981 clock-names = "apb_pclk";
986 compatible = "arm,coresight-cpu-debug","arm,primecell";
989 clock-names = "apb_pclk";
994 compatible = "arm,coresight-cpu-debug","arm,primecell";
997 clock-names = "apb_pclk";
1002 compatible = "arm,coresight-cpu-debug","arm,primecell";
1005 clock-names = "apb_pclk";
1010 compatible = "arm,coresight-cpu-debug","arm,primecell";
1013 clock-names = "apb_pclk";
1018 compatible = "arm,coresight-cpu-debug","arm,primecell";
1021 clock-names = "apb_pclk";
1027 #include "hi6220-coresight.dtsi"