Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mm-pinfunc.h"
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
44 #address-cells = <1>;
45 #size-cells = <0>;
47 idle-states {
48 entry-method = "psci";
50 cpu_pd_wait: cpu-pd-wait {
51 compatible = "arm,idle-state";
52 arm,psci-suspend-param = <0x0010033>;
53 local-timer-stop;
54 entry-latency-us = <1000>;
55 exit-latency-us = <700>;
56 min-residency-us = <2700>;
62 compatible = "arm,cortex-a53";
64 clock-latency = <61036>; /* two CLK32 periods */
66 enable-method = "psci";
67 next-level-cache = <&A53_L2>;
68 operating-points-v2 = <&a53_opp_table>;
69 nvmem-cells = <&cpu_speed_grade>;
70 nvmem-cell-names = "speed_grade";
71 cpu-idle-states = <&cpu_pd_wait>;
76 compatible = "arm,cortex-a53";
78 clock-latency = <61036>; /* two CLK32 periods */
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
82 operating-points-v2 = <&a53_opp_table>;
83 cpu-idle-states = <&cpu_pd_wait>;
88 compatible = "arm,cortex-a53";
90 clock-latency = <61036>; /* two CLK32 periods */
92 enable-method = "psci";
93 next-level-cache = <&A53_L2>;
94 operating-points-v2 = <&a53_opp_table>;
95 cpu-idle-states = <&cpu_pd_wait>;
100 compatible = "arm,cortex-a53";
102 clock-latency = <61036>; /* two CLK32 periods */
104 enable-method = "psci";
105 next-level-cache = <&A53_L2>;
106 operating-points-v2 = <&a53_opp_table>;
107 cpu-idle-states = <&cpu_pd_wait>;
110 A53_L2: l2-cache0 {
115 a53_opp_table: opp-table {
116 compatible = "operating-points-v2";
117 opp-shared;
119 opp-1200000000 {
120 opp-hz = /bits/ 64 <1200000000>;
121 opp-microvolt = <850000>;
122 opp-supported-hw = <0xe>, <0x7>;
123 clock-latency-ns = <150000>;
124 opp-suspend;
127 opp-1600000000 {
128 opp-hz = /bits/ 64 <1600000000>;
129 opp-microvolt = <900000>;
130 opp-supported-hw = <0xc>, <0x7>;
131 clock-latency-ns = <150000>;
132 opp-suspend;
135 opp-1800000000 {
136 opp-hz = /bits/ 64 <1800000000>;
137 opp-microvolt = <1000000>;
138 opp-supported-hw = <0x8>, <0x3>;
139 clock-latency-ns = <150000>;
140 opp-suspend;
149 osc_32k: clock-osc-32k {
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
152 clock-frequency = <32768>;
153 clock-output-names = "osc_32k";
156 osc_24m: clock-osc-24m {
157 compatible = "fixed-clock";
158 #clock-cells = <0>;
159 clock-frequency = <24000000>;
160 clock-output-names = "osc_24m";
163 clk_ext1: clock-ext1 {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <133000000>;
167 clock-output-names = "clk_ext1";
170 clk_ext2: clock-ext2 {
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <133000000>;
174 clock-output-names = "clk_ext2";
177 clk_ext3: clock-ext3 {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <133000000>;
181 clock-output-names = "clk_ext3";
184 clk_ext4: clock-ext4 {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency= <133000000>;
188 clock-output-names = "clk_ext4";
191 psci {
192 compatible = "arm,psci-1.0";
197 compatible = "arm,armv8-pmuv3";
200 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
204 compatible = "arm,armv8-timer";
206 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
209 clock-frequency = <8000000>;
210 arm,no-tick-in-suspend;
214 compatible = "usb-nop-xceiv";
216 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
217 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
218 clock-names = "main_clk";
222 compatible = "usb-nop-xceiv";
224 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
225 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
226 clock-names = "main_clk";
230 compatible = "simple-bus";
231 #address-cells = <1>;
232 #size-cells = <1>;
236 compatible = "fsl,aips-bus", "simple-bus";
237 #address-cells = <1>;
238 #size-cells = <1>;
242 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
248 clock-names = "bus", "mclk1", "mclk2", "mclk3";
250 dma-names = "rx", "tx";
255 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
261 clock-names = "bus", "mclk1", "mclk2", "mclk3";
263 dma-names = "rx", "tx";
268 #sound-dai-cells = <0>;
269 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
275 clock-names = "bus", "mclk1", "mclk2", "mclk3";
277 dma-names = "rx", "tx";
282 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
288 clock-names = "bus", "mclk1", "mclk2", "mclk3";
290 dma-names = "rx", "tx";
295 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
301 clock-names = "bus", "mclk1", "mclk2", "mclk3";
303 dma-names = "rx", "tx";
308 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 gpio-ranges = <&iomuxc 0 10 30>;
321 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
326 gpio-controller;
327 #gpio-cells = <2>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
330 gpio-ranges = <&iomuxc 0 40 21>;
334 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
339 gpio-controller;
340 #gpio-cells = <2>;
341 interrupt-controller;
342 #interrupt-cells = <2>;
343 gpio-ranges = <&iomuxc 0 61 26>;
347 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 gpio-ranges = <&iomuxc 0 87 32>;
360 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
365 gpio-controller;
366 #gpio-cells = <2>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 gpio-ranges = <&iomuxc 0 119 30>;
373 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
381 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
389 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
396 sdma2: dma-controller@302c0000 {
397 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
402 clock-names = "ipg", "ahb";
403 #dma-cells = <3>;
404 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
407 sdma3: dma-controller@302b0000 {
408 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
413 clock-names = "ipg", "ahb";
414 #dma-cells = <3>;
415 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
419 compatible = "fsl,imx8mm-iomuxc";
423 gpr: iomuxc-gpr@30340000 {
424 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
428 ocotp: ocotp-ctrl@30350000 {
429 compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
433 #address-cells = <1>;
434 #size-cells = <1>;
436 cpu_speed_grade: speed-grade@10 {
442 compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
447 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
450 snvs_rtc: snvs-rtc-lp {
451 compatible = "fsl,sec-v4.0-mon-rtc-lp";
457 clock-names = "snvs-rtc";
460 snvs_pwrkey: snvs-powerkey {
461 compatible = "fsl,sec-v4.0-pwrkey";
465 wakeup-source;
470 clk: clock-controller@30380000 {
471 compatible = "fsl,imx8mm-ccm";
473 #clock-cells = <1>;
476 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
478 assigned-clocks = <&clk IMX8MM_CLK_NOC>,
483 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
485 assigned-clock-rates = <0>,
492 src: reset-controller@30390000 {
493 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
496 #reset-cells = <1>;
501 compatible = "fsl,aips-bus", "simple-bus";
502 #address-cells = <1>;
503 #size-cells = <1>;
507 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
512 clock-names = "ipg", "per";
513 #pwm-cells = <2>;
518 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
523 clock-names = "ipg", "per";
524 #pwm-cells = <2>;
529 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
534 clock-names = "ipg", "per";
535 #pwm-cells = <2>;
540 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
545 clock-names = "ipg", "per";
546 #pwm-cells = <2>;
551 compatible = "nxp,sysctr-timer";
555 clock-names = "per";
560 compatible = "fsl,aips-bus", "simple-bus";
561 #address-cells = <1>;
562 #size-cells = <1>;
566 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
567 #address-cells = <1>;
568 #size-cells = <0>;
573 clock-names = "ipg", "per";
575 dma-names = "rx", "tx";
580 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
581 #address-cells = <1>;
582 #size-cells = <0>;
587 clock-names = "ipg", "per";
589 dma-names = "rx", "tx";
594 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
595 #address-cells = <1>;
596 #size-cells = <0>;
601 clock-names = "ipg", "per";
603 dma-names = "rx", "tx";
608 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
613 clock-names = "ipg", "per";
615 dma-names = "rx", "tx";
620 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
625 clock-names = "ipg", "per";
627 dma-names = "rx", "tx";
632 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
637 clock-names = "ipg", "per";
642 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
643 #address-cells = <1>;
644 #size-cells = <0>;
652 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
653 #address-cells = <1>;
654 #size-cells = <0>;
662 #address-cells = <1>;
663 #size-cells = <0>;
664 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
672 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
673 #address-cells = <1>;
674 #size-cells = <0>;
682 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
687 clock-names = "ipg", "per";
689 dma-names = "rx", "tx";
694 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
700 clock-names = "ipg", "ahb", "per";
701 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
702 assigned-clock-rates = <400000000>;
703 fsl,tuning-start-tap = <20>;
704 fsl,tuning-step= <2>;
705 bus-width = <4>;
710 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
716 clock-names = "ipg", "ahb", "per";
717 fsl,tuning-start-tap = <20>;
718 fsl,tuning-step= <2>;
719 bus-width = <4>;
724 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
730 clock-names = "ipg", "ahb", "per";
731 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
732 assigned-clock-rates = <400000000>;
733 fsl,tuning-start-tap = <20>;
734 fsl,tuning-step= <2>;
735 bus-width = <4>;
739 sdma1: dma-controller@30bd0000 {
740 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
745 clock-names = "ipg", "ahb";
746 #dma-cells = <3>;
747 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
751 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
761 clock-names = "ipg", "ahb", "ptp",
763 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
767 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
770 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
771 fsl,num-tx-queues = <3>;
772 fsl,num-rx-queues = <3>;
779 compatible = "fsl,aips-bus", "simple-bus";
780 #address-cells = <1>;
781 #size-cells = <1>;
785 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
789 clock-names = "usb1_ctrl_root_clk";
790 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
791 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
798 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
799 #index-cells = <1>;
804 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
808 clock-names = "usb1_ctrl_root_clk";
809 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
810 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
817 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
818 #index-cells = <1>;
824 dma_apbh: dma-controller@33000000 {
825 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
831 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
832 #dma-cells = <1>;
833 dma-channels = <4>;
837 gpmi: nand-controller@33002000{
838 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
839 #address-cells = <1>;
840 #size-cells = <1>;
842 reg-names = "gpmi-nand", "bch";
844 interrupt-names = "bch";
847 clock-names = "gpmi_io", "gpmi_bch_apb";
849 dma-names = "rx-tx";
853 gic: interrupt-controller@38800000 {
854 compatible = "arm,gic-v3";
857 #interrupt-cells = <3>;
858 interrupt-controller;
862 ddr-pmu@3d800000 {
863 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
865 interrupt-parent = <&gic>;