Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 // 8 clusters having 2 Cortex-A72 cores each
25 compatible = "arm,cortex-a72";
26 enable-method = "psci";
29 d-cache-size = <0x8000>;
30 d-cache-line-size = <64>;
31 d-cache-sets = <128>;
32 i-cache-size = <0xC000>;
33 i-cache-line-size = <64>;
34 i-cache-sets = <192>;
35 next-level-cache = <&cluster0_l2>;
36 cpu-idle-states = <&cpu_pw15>;
41 compatible = "arm,cortex-a72";
42 enable-method = "psci";
45 d-cache-size = <0x8000>;
46 d-cache-line-size = <64>;
47 d-cache-sets = <128>;
48 i-cache-size = <0xC000>;
49 i-cache-line-size = <64>;
50 i-cache-sets = <192>;
51 next-level-cache = <&cluster0_l2>;
52 cpu-idle-states = <&cpu_pw15>;
57 compatible = "arm,cortex-a72";
58 enable-method = "psci";
61 d-cache-size = <0x8000>;
62 d-cache-line-size = <64>;
63 d-cache-sets = <128>;
64 i-cache-size = <0xC000>;
65 i-cache-line-size = <64>;
66 i-cache-sets = <192>;
67 next-level-cache = <&cluster1_l2>;
68 cpu-idle-states = <&cpu_pw15>;
73 compatible = "arm,cortex-a72";
74 enable-method = "psci";
77 d-cache-size = <0x8000>;
78 d-cache-line-size = <64>;
79 d-cache-sets = <128>;
80 i-cache-size = <0xC000>;
81 i-cache-line-size = <64>;
82 i-cache-sets = <192>;
83 next-level-cache = <&cluster1_l2>;
84 cpu-idle-states = <&cpu_pw15>;
89 compatible = "arm,cortex-a72";
90 enable-method = "psci";
93 d-cache-size = <0x8000>;
94 d-cache-line-size = <64>;
95 d-cache-sets = <128>;
96 i-cache-size = <0xC000>;
97 i-cache-line-size = <64>;
98 i-cache-sets = <192>;
99 next-level-cache = <&cluster2_l2>;
100 cpu-idle-states = <&cpu_pw15>;
105 compatible = "arm,cortex-a72";
106 enable-method = "psci";
109 d-cache-size = <0x8000>;
110 d-cache-line-size = <64>;
111 d-cache-sets = <128>;
112 i-cache-size = <0xC000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <192>;
115 next-level-cache = <&cluster2_l2>;
116 cpu-idle-states = <&cpu_pw15>;
121 compatible = "arm,cortex-a72";
122 enable-method = "psci";
125 d-cache-size = <0x8000>;
126 d-cache-line-size = <64>;
127 d-cache-sets = <128>;
128 i-cache-size = <0xC000>;
129 i-cache-line-size = <64>;
130 i-cache-sets = <192>;
131 next-level-cache = <&cluster3_l2>;
132 cpu-idle-states = <&cpu_pw15>;
137 compatible = "arm,cortex-a72";
138 enable-method = "psci";
141 d-cache-size = <0x8000>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <128>;
144 i-cache-size = <0xC000>;
145 i-cache-line-size = <64>;
146 i-cache-sets = <192>;
147 next-level-cache = <&cluster3_l2>;
148 cpu-idle-states = <&cpu_pw15>;
153 compatible = "arm,cortex-a72";
154 enable-method = "psci";
157 d-cache-size = <0x8000>;
158 d-cache-line-size = <64>;
159 d-cache-sets = <128>;
160 i-cache-size = <0xC000>;
161 i-cache-line-size = <64>;
162 i-cache-sets = <192>;
163 next-level-cache = <&cluster4_l2>;
164 cpu-idle-states = <&cpu_pw15>;
169 compatible = "arm,cortex-a72";
170 enable-method = "psci";
173 d-cache-size = <0x8000>;
174 d-cache-line-size = <64>;
175 d-cache-sets = <128>;
176 i-cache-size = <0xC000>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <192>;
179 next-level-cache = <&cluster4_l2>;
180 cpu-idle-states = <&cpu_pw15>;
185 compatible = "arm,cortex-a72";
186 enable-method = "psci";
189 d-cache-size = <0x8000>;
190 d-cache-line-size = <64>;
191 d-cache-sets = <128>;
192 i-cache-size = <0xC000>;
193 i-cache-line-size = <64>;
194 i-cache-sets = <192>;
195 next-level-cache = <&cluster5_l2>;
196 cpu-idle-states = <&cpu_pw15>;
201 compatible = "arm,cortex-a72";
202 enable-method = "psci";
205 d-cache-size = <0x8000>;
206 d-cache-line-size = <64>;
207 d-cache-sets = <128>;
208 i-cache-size = <0xC000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <192>;
211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cpu_pw15>;
217 compatible = "arm,cortex-a72";
218 enable-method = "psci";
221 d-cache-size = <0x8000>;
222 d-cache-line-size = <64>;
223 d-cache-sets = <128>;
224 i-cache-size = <0xC000>;
225 i-cache-line-size = <64>;
226 i-cache-sets = <192>;
227 next-level-cache = <&cluster6_l2>;
228 cpu-idle-states = <&cpu_pw15>;
233 compatible = "arm,cortex-a72";
234 enable-method = "psci";
237 d-cache-size = <0x8000>;
238 d-cache-line-size = <64>;
239 d-cache-sets = <128>;
240 i-cache-size = <0xC000>;
241 i-cache-line-size = <64>;
242 i-cache-sets = <192>;
243 next-level-cache = <&cluster6_l2>;
244 cpu-idle-states = <&cpu_pw15>;
249 compatible = "arm,cortex-a72";
250 enable-method = "psci";
253 d-cache-size = <0x8000>;
254 d-cache-line-size = <64>;
255 d-cache-sets = <128>;
256 i-cache-size = <0xC000>;
257 i-cache-line-size = <64>;
258 i-cache-sets = <192>;
259 next-level-cache = <&cluster7_l2>;
260 cpu-idle-states = <&cpu_pw15>;
265 compatible = "arm,cortex-a72";
266 enable-method = "psci";
269 d-cache-size = <0x8000>;
270 d-cache-line-size = <64>;
271 d-cache-sets = <128>;
272 i-cache-size = <0xC000>;
273 i-cache-line-size = <64>;
274 i-cache-sets = <192>;
275 next-level-cache = <&cluster7_l2>;
276 cpu-idle-states = <&cpu_pw15>;
279 cluster0_l2: l2-cache0 {
281 cache-size = <0x100000>;
282 cache-line-size = <64>;
283 cache-sets = <1024>;
284 cache-level = <2>;
287 cluster1_l2: l2-cache1 {
289 cache-size = <0x100000>;
290 cache-line-size = <64>;
291 cache-sets = <1024>;
292 cache-level = <2>;
295 cluster2_l2: l2-cache2 {
297 cache-size = <0x100000>;
298 cache-line-size = <64>;
299 cache-sets = <1024>;
300 cache-level = <2>;
303 cluster3_l2: l2-cache3 {
305 cache-size = <0x100000>;
306 cache-line-size = <64>;
307 cache-sets = <1024>;
308 cache-level = <2>;
311 cluster4_l2: l2-cache4 {
313 cache-size = <0x100000>;
314 cache-line-size = <64>;
315 cache-sets = <1024>;
316 cache-level = <2>;
319 cluster5_l2: l2-cache5 {
321 cache-size = <0x100000>;
322 cache-line-size = <64>;
323 cache-sets = <1024>;
324 cache-level = <2>;
327 cluster6_l2: l2-cache6 {
329 cache-size = <0x100000>;
330 cache-line-size = <64>;
331 cache-sets = <1024>;
332 cache-level = <2>;
335 cluster7_l2: l2-cache7 {
337 cache-size = <0x100000>;
338 cache-line-size = <64>;
339 cache-sets = <1024>;
340 cache-level = <2>;
343 cpu_pw15: cpu-pw15 {
344 compatible = "arm,idle-state";
345 idle-state-name = "PW15";
346 arm,psci-suspend-param = <0x0>;
347 entry-latency-us = <2000>;
348 exit-latency-us = <2000>;
349 min-residency-us = <6000>;
353 gic: interrupt-controller@6000000 {
354 compatible = "arm,gic-v3";
361 #interrupt-cells = <3>;
362 #address-cells = <2>;
363 #size-cells = <2>;
365 interrupt-controller;
368 its: gic-its@6020000 {
369 compatible = "arm,gic-v3-its";
370 msi-controller;
376 compatible = "arm,armv8-timer";
384 compatible = "arm,cortex-a72-pmu";
388 psci {
389 compatible = "arm,psci-0.2";
394 // DRAM space - 1, size : 2 GB DRAM
399 ddr1: memory-controller@1080000 {
400 compatible = "fsl,qoriq-memory-controller";
403 little-endian;
406 ddr2: memory-controller@1090000 {
407 compatible = "fsl,qoriq-memory-controller";
410 little-endian;
413 // One clock unit-sysclk node which bootloader require during DT fix-up
415 compatible = "fixed-clock";
416 #clock-cells = <0>;
417 clock-frequency = <100000000>; // fixed up by bootloader
418 clock-output-names = "sysclk";
422 compatible = "simple-bus";
423 #address-cells = <2>;
424 #size-cells = <2>;
426 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
429 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
430 fsl,sec-era = <10>;
431 #address-cells = <1>;
432 #size-cells = <1>;
436 dma-coherent;
440 compatible = "fsl,sec-v5.0-job-ring",
441 "fsl,sec-v4.0-job-ring";
447 compatible = "fsl,sec-v5.0-job-ring",
448 "fsl,sec-v4.0-job-ring";
454 compatible = "fsl,sec-v5.0-job-ring",
455 "fsl,sec-v4.0-job-ring";
461 compatible = "fsl,sec-v5.0-job-ring",
462 "fsl,sec-v4.0-job-ring";
468 clockgen: clock-controller@1300000 {
469 compatible = "fsl,lx2160a-clockgen";
471 #clock-cells = <2>;
476 compatible = "fsl,lx2160a-dcfg", "syscon";
478 little-endian;
482 compatible = "fsl,vf610-i2c";
483 #address-cells = <1>;
484 #size-cells = <0>;
487 clock-names = "i2c";
489 scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
494 compatible = "fsl,vf610-i2c";
495 #address-cells = <1>;
496 #size-cells = <0>;
499 clock-names = "i2c";
505 compatible = "fsl,vf610-i2c";
506 #address-cells = <1>;
507 #size-cells = <0>;
510 clock-names = "i2c";
516 compatible = "fsl,vf610-i2c";
517 #address-cells = <1>;
518 #size-cells = <0>;
521 clock-names = "i2c";
527 compatible = "fsl,vf610-i2c";
528 #address-cells = <1>;
529 #size-cells = <0>;
532 clock-names = "i2c";
534 scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
539 compatible = "fsl,vf610-i2c";
540 #address-cells = <1>;
541 #size-cells = <0>;
544 clock-names = "i2c";
550 compatible = "fsl,vf610-i2c";
551 #address-cells = <1>;
552 #size-cells = <0>;
555 clock-names = "i2c";
561 compatible = "fsl,vf610-i2c";
562 #address-cells = <1>;
563 #size-cells = <0>;
566 clock-names = "i2c";
572 compatible = "nxp,lx2160a-fspi";
573 #address-cells = <1>;
574 #size-cells = <0>;
577 reg-names = "fspi_base", "fspi_mmap";
580 clock-names = "fspi_en", "fspi";
589 voltage-ranges = <1800 1800 3300 3300>;
590 sdhci,auto-cmd12;
591 little-endian;
592 bus-width = <4>;
601 voltage-ranges = <1800 1800 3300 3300>;
602 sdhci,auto-cmd12;
603 broken-cd;
604 little-endian;
605 bus-width = <4>;
610 compatible = "arm,sbsa-uart","arm,pl011";
613 current-speed = <115200>;
618 compatible = "arm,sbsa-uart","arm,pl011";
621 current-speed = <115200>;
626 compatible = "arm,sbsa-uart","arm,pl011";
629 current-speed = <115200>;
634 compatible = "arm,sbsa-uart","arm,pl011";
637 current-speed = <115200>;
642 compatible = "fsl,qoriq-gpio";
645 gpio-controller;
646 little-endian;
647 #gpio-cells = <2>;
648 interrupt-controller;
649 #interrupt-cells = <2>;
653 compatible = "fsl,qoriq-gpio";
656 gpio-controller;
657 little-endian;
658 #gpio-cells = <2>;
659 interrupt-controller;
660 #interrupt-cells = <2>;
664 compatible = "fsl,qoriq-gpio";
667 gpio-controller;
668 little-endian;
669 #gpio-cells = <2>;
670 interrupt-controller;
671 #interrupt-cells = <2>;
675 compatible = "fsl,qoriq-gpio";
678 gpio-controller;
679 little-endian;
680 #gpio-cells = <2>;
681 interrupt-controller;
682 #interrupt-cells = <2>;
686 compatible = "arm,sbsa-gwdt";
690 timeout-sec = <30>;
698 snps,quirk-frame-length-adjustment = <0x20>;
700 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
709 snps,quirk-frame-length-adjustment = <0x20>;
711 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
716 compatible = "fsl,lx2160a-ahci";
719 reg-names = "ahci", "sata-ecc";
722 dma-coherent;
727 compatible = "fsl,lx2160a-ahci";
730 reg-names = "ahci", "sata-ecc";
733 dma-coherent;
738 compatible = "fsl,lx2160a-ahci";
741 reg-names = "ahci", "sata-ecc";
744 dma-coherent;
749 compatible = "fsl,lx2160a-ahci";
752 reg-names = "ahci", "sata-ecc";
755 dma-coherent;
760 compatible = "arm,mmu-500";
762 #iommu-cells = <1>;
763 #global-interrupts = <14>;
768 // global non-secure fault
770 // combined non-secure
772 // performance counter interrupts 0-9
848 dma-coherent;
852 compatible = "fsl,dpaa2-console";
856 ptp-timer@8b95000 {
857 compatible = "fsl,dpaa2-ptp";
860 little-endian;
861 fsl,extts-fifo;
864 fsl_mc: fsl-mc@80c000000 {
865 compatible = "fsl,qoriq-mc";
868 msi-parent = <&its>;
869 /* iommu-map property is fixed up by u-boot */
870 iommu-map = <0 &smmu 0 0>;
871 dma-coherent;
872 #address-cells = <3>;
873 #size-cells = <1>;
876 * Region type 0x0 - MC portals
877 * Region type 0x1 - QBMAN portals
886 #address-cells = <1>;
887 #size-cells = <0>;
890 compatible = "fsl,qoriq-mc-dpmac";
895 compatible = "fsl,qoriq-mc-dpmac";
900 compatible = "fsl,qoriq-mc-dpmac";
905 compatible = "fsl,qoriq-mc-dpmac";
910 compatible = "fsl,qoriq-mc-dpmac";
915 compatible = "fsl,qoriq-mc-dpmac";
920 compatible = "fsl,qoriq-mc-dpmac";
925 compatible = "fsl,qoriq-mc-dpmac";
930 compatible = "fsl,qoriq-mc-dpmac";
935 compatible = "fsl,qoriq-mc-dpmac";
940 compatible = "fsl,qoriq-mc-dpmac";
945 compatible = "fsl,qoriq-mc-dpmac";
950 compatible = "fsl,qoriq-mc-dpmac";
955 compatible = "fsl,qoriq-mc-dpmac";
960 compatible = "fsl,qoriq-mc-dpmac";
965 compatible = "fsl,qoriq-mc-dpmac";
970 compatible = "fsl,qoriq-mc-dpmac";
975 compatible = "fsl,qoriq-mc-dpmac";