Lines Matching +full:phy +full:- +full:handle
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
10 /dts-v1/;
12 #include "fsl-ls1046a.dtsi"
16 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
26 stdout-path = "serial0:115200n8";
39 mmc-hs200-1_8v;
40 sd-uhs-sdr104;
41 sd-uhs-sdr50;
42 sd-uhs-sdr25;
43 sd-uhs-sdr12;
52 shunt-resistor = <1000>;
55 temp-sensor@4c {
81 #address-cells = <2>;
82 #size-cells = <1>;
89 compatible = "fsl,ifc-nand";
90 #address-cells = <1>;
91 #size-cells = <1>;
95 cpld: board-control@2,0 {
96 compatible = "fsl,ls1046ardb-cpld";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 spi-max-frequency = <20000000>;
109 spi-rx-bus-width = <4>;
110 spi-tx-bus-width = <4>;
116 #address-cells = <1>;
117 #size-cells = <1>;
118 spi-max-frequency = <20000000>;
119 spi-rx-bus-width = <4>;
120 spi-tx-bus-width = <4>;
125 #include "fsl-ls1046-post.dtsi"
129 phy-handle = <&rgmii_phy1>;
130 phy-connection-type = "rgmii";
134 phy-handle = <&rgmii_phy2>;
135 phy-connection-type = "rgmii";
139 phy-handle = <&sgmii_phy1>;
140 phy-connection-type = "sgmii";
144 phy-handle = <&sgmii_phy2>;
145 phy-connection-type = "sgmii";
149 phy-handle = <&aqr106_phy>;
150 phy-connection-type = "xgmii";
154 fixed-link = <0 1 1000 0 0>;
155 phy-connection-type = "xgmii";
159 rgmii_phy1: ethernet-phy@1 {
163 rgmii_phy2: ethernet-phy@2 {
167 sgmii_phy1: ethernet-phy@3 {
171 sgmii_phy2: ethernet-phy@4 {
177 aqr106_phy: ethernet-phy@0 {
178 compatible = "ethernet-phy-ieee802.3-c45";