Lines Matching +full:ethernet +full:- +full:phy

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5  * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
25 		stdout-path = "serial0:115200n8";
34 		shunt-resistor = <1000>;
56 	#address-cells = <2>;
57 	#size-cells = <1>;
64 			compatible = "cfi-flash";
65 			#address-cells = <1>;
66 			#size-cells = <1>;
68 			big-endian;
69 			bank-width = <2>;
70 			device-width = <1>;
74 			compatible = "fsl,ifc-nand";
75 			#address-cells = <1>;
76 			#size-cells = <1>;
80 		cpld: board-control@2,0 {
81 			compatible = "fsl,ls1043ardb-cpld";
87 	bus-num = <0>;
91 		#address-cells = <1>;
92 		#size-cells = <1>;
93 		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
95 		spi-max-frequency = <1000000>; /* input clock */
107 #include "fsl-ls1043-post.dtsi"
110 	ethernet@e0000 {
111 		phy-handle = <&qsgmii_phy1>;
112 		phy-connection-type = "qsgmii";
115 	ethernet@e2000 {
116 		phy-handle = <&qsgmii_phy2>;
117 		phy-connection-type = "qsgmii";
120 	ethernet@e4000 {
121 		phy-handle = <&rgmii_phy1>;
122 		phy-connection-type = "rgmii-txid";
125 	ethernet@e6000 {
126 		phy-handle = <&rgmii_phy2>;
127 		phy-connection-type = "rgmii-txid";
130 	ethernet@e8000 {
131 		phy-handle = <&qsgmii_phy3>;
132 		phy-connection-type = "qsgmii";
135 	ethernet@ea000 {
136 		phy-handle = <&qsgmii_phy4>;
137 		phy-connection-type = "qsgmii";
140 	ethernet@f0000 { /* 10GEC1 */
141 		phy-handle = <&aqr105_phy>;
142 		phy-connection-type = "xgmii";
146 		rgmii_phy1: ethernet-phy@1 {
150 		rgmii_phy2: ethernet-phy@2 {
154 		qsgmii_phy1: ethernet-phy@4 {
158 		qsgmii_phy2: ethernet-phy@5 {
162 		qsgmii_phy3: ethernet-phy@6 {
166 		qsgmii_phy4: ethernet-phy@7 {
172 		aqr105_phy: ethernet-phy@1 {
173 			compatible = "ethernet-phy-ieee802.3-c45";