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1 # SPDX-License-Identifier: GPL-2.0-only
189 ARM 64-bit (AArch64) Linux support.
215 # VA_BITS - PAGE_SHIFT - 3
325 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
329 This option adds an alternative code sequence to work around ARM
330 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
333 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
339 data cache clean-and-invalidate.
347 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
351 This option adds an alternative code sequence to work around ARM
352 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
361 data cache clean-and-invalidate.
369 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
373 This option adds an alternative code sequence to work around ARM
374 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
377 If a Cortex-A53 processor is executing a store or prefetch for
384 data cache clean-and-invalidate.
392 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
396 This option adds an alternative code sequence to work around ARM
397 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
406 data cache clean-and-invalidate.
414 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
417 This option adds an alternative code sequence to work around ARM
418 erratum 832075 on Cortex-A57 parts up to r1p2.
420 Affected Cortex-A57 parts might deadlock when exclusive load/store
421 instructions to Write-Back memory are mixed with Device loads.
423 The workaround is to promote device loads to use Load-Acquire
432 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
436 This option adds an alternative code sequence to work around ARM
437 erratum 834220 on Cortex-A57 parts up to r1p2.
439 Affected Cortex-A57 parts might report a Stage 2 translation
453 bool "Cortex-A53: 845719: a load might read incorrect data"
457 This option adds an alternative code sequence to work around ARM
458 erratum 845719 on Cortex-A53 parts up to r0p4.
460 When running a compat (AArch32) userspace on an affected Cortex-A53
466 return to a 32-bit task.
474 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
478 This option links the kernel with '--fix-cortex-a53-843419' and
481 Cortex-A53 parts up to r0p4.
486 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
489 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
491 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
493 without a break-before-make. The workaround is to disable the usage
500 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
504 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
507 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
514 …bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause s…
517 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
519 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
526 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
530 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
532 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
536 break-before-make sequence, then under very rare circumstances
544 bool "Cortex-A76: Software Step might prevent interrupt recognition"
547 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
549 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
555 Work around the erratum by triggering a dummy step exception
567 This implements two gicv3-its errata workarounds for ThunderX. Both
603 contains data for a non-current ASID. The fix is to
614 interrupts in host. Trapping both GICv3 group-0 and group-1
628 Work around the issue by avoiding the problematic code sequence and
644 is unchanged. Work around the erratum by invalidating the walk cache
672 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
676 MSI doorbell writes with non-zero values for the device ID.
701 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
704 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
705 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
709 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
710 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
711 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
712 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
715 The workaround only affects the Fujitsu-A64FX.
745 look-up. AArch32 emulation requires applications compiled
761 bool "36-bit" if EXPERT
765 bool "39-bit"
769 bool "42-bit"
773 bool "47-bit"
777 bool "48-bit"
780 bool "52-bit"
783 Enable 52-bit virtual addressing for userspace when explicitly
784 requested via a hint to mmap(). The kernel will also use 52-bit
786 this feature is available, otherwise it reverts to 48-bit).
788 NOTE: Enabling 52-bit virtual addressing in conjunction with
791 impact on its susceptibility to brute-force attacks.
793 If unsure, select 48-bit virtual addressing instead.
798 bool "Force 52-bit virtual addresses for userspace"
801 For systems with 52-bit userspace VAs enabled, the kernel will attempt
802 to maintain compatibility with older software by providing 48-bit VAs
805 This configuration option disables the 48-bit compatibility logic, and
806 forces all userspace addresses to be 52-bit on HW that supports it. One
827 bool "48-bit"
830 bool "52-bit (ARMv8.2)"
834 Enable support for a 52-bit physical address space, introduced as
835 part of the ARMv8.2-LPA extension.
838 do not support ARMv8.2-LPA, but with some added memory overhead (and
849 bool "Build big-endian kernel"
851 Say Y if you plan on running a kernel in big-endian mode.
854 bool "Multi-core scheduler support"
856 Multi-core scheduler support improves the CPU scheduler's decision
857 making when dealing with multi-core CPU chips at a cost of slightly
868 int "Maximum number of CPUs (2-4096)"
873 bool "Support for hot-pluggable CPUs"
953 ---help---
986 ---help---
1030 loaded in the main kernel with kexec-tools into a specially
1034 For more details see Documentation/admin-guide/kdump/kdump.rst
1066 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1075 Speculation attacks against some high-performance processors can
1087 Speculation attacks against some high-performance processors rely on
1093 This config option will take CPU-specific actions to harden the
1104 Speculation attacks against some high-performance processors can
1129 Apply read-only attributes of VM areas to the linear alias of
1130 the backing pages as well. This prevents code or read-only data
1143 user-space memory directly by pointing TTBR0_EL1 to a reserved
1154 Documentation/arm64/tagged-address-abi.rst.
1157 bool "Kernel support for 32-bit EL0"
1164 This option enables support for a 32-bit EL0 running under a 64-bit
1165 kernel at EL1. AArch32-specific components such as system calls,
1173 If you want to execute 32-bit userspace applications, say Y.
1178 bool "Enable kuser helpers page for 32-bit applications"
1181 Warning: disabling this option may break 32-bit user programs.
1197 these helpers, then you can turn this option off to hinder
1205 bool "Enable vDSO for 32-bit applications"
1210 Place in the process address space of 32-bit applications an
1214 You must have a 32-bit build of glibc 2.22 or later for programs
1255 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1256 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1270 The SETEND instruction alters the data-endianness of the
1277 for this feature to be enabled. If a new CPU - which doesn't support mixed
1278 endian - is hotplugged in after this feature has been enabled, there could
1297 Similarly, writes to read-only pages with the DBM bit set will
1298 clear the read-only bit (AP[2]) instead of raising a
1302 to work on pre-ARMv8.1 hardware and the performance impact is
1310 prevents the kernel or hypervisor from accessing user-space (EL0)
1328 Say Y here to make use of these instructions for the in-kernel
1360 variant of the load/store instructions. This ensures that user-space
1365 Choosing this option will cause copy_to_user() et al to use user-space
1432 context-switched along with the process.
1467 If you need the kernel to boot on SVE-capable hardware with broken
1500 bool "Support for NMI-like interrupts"
1503 Adds support for mimicking Non-Maskable Interrupts through the use of
1546 random u64 value in /chosen/kaslr-seed at kernel entry.
1571 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
1594 Provide a set of default command-line options at build time by
1604 command-line options your boot loader passes to the kernel.
1623 by UEFI firmware (such as non-volatile variables, realtime
1637 continue to boot on existing non-UEFI platforms.