Lines Matching refs:c7
58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
110 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
111 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
113 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
127 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
129 mcr p15, 0, r0, c7, c10, 4 @ drain WB
137 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
138 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
140 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
142 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
149 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
150 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush