Lines Matching refs:context_offs

57 			.context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
78 			.context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
92 			.context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
105 			.context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
127 			.context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
179 			.context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
202 			.context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
226 			.context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
261 			.context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
306 			.context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
322 			.context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
356 			.context_offs	= DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
371 			.context_offs	= DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
386 			.context_offs	= DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
431 			.context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
453 			.context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
476 			.context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
492 			.context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
535 			.context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
652 			.context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
667 			.context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
694 			.context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
732 			.context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
769 			.context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
805 			.context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
838 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
851 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
864 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
877 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
890 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
903 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
916 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
929 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
942 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
955 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
968 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
981 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
994 			.context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1018 			.context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1052 			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1067 			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1121 			.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1144 			.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1178 			.context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1213 			.context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1251 			.context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1291 			.context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1312 			.context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1349 			.context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1400 			.context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1415 			.context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1430 			.context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1445 			.context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1460 			.context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1475 			.context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1490 			.context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1505 			.context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1520 			.context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1535 			.context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1550 			.context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1565 			.context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
1579 			.context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1594 			.context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1609 			.context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
1624 			.context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
1652 			.context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
1680 			.context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
1721 			.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
1743 			.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
1760 			.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
1775 			.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
1799 			.context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
1813 			.context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
1850 			.context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,