Lines Matching refs:r12
75 ldr r12, [r10, #PROCINFO_INITFUNC]
76 add r12, r12, r10
77 ret r12
113 ldr r12, [r10, #PROCINFO_INITFUNC]
114 add r12, r12, r10
115 ret r12
132 M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
133 M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
135 M_CLASS(ldr r3, [r12, 0x50])
152 M_CLASS(streq r3, [r12, #PMSAv8_MAIR0])
155 M_CLASS(streq r3, [r12, #PMSAv8_MAIR1])
187 ldreq r3, [r12, MPU_CTRL]
190 streq r3, [r12, MPU_CTRL]
203 str r0, [r12, V7M_SCB_CCR]
255 M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
256 M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
259 M_CLASS(ldr r0, [r12, 0x50])
282 M_CLASS(ldr r0, [r12, #MPU_TYPE])
288 set_region_nr r0, #PMSAv7_RAM_REGION, r12
294 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ PHYS_OFFSET, shared, enabled
296 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ PHYS_OFFSET, shared, enabled
300 set_region_nr r0, #PMSAv7_BG_REGION, r12
307 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ 0x0, BG region, enabled
309 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE r12 @ 0x0, BG region, enabled
313 set_region_nr r0, #PMSAv7_ROM_REGION, r12
326 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
328 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
337 M_CLASS(str r0, [r12, #PMSAv8_RNR])
351 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(0)])
352 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(0)])
365 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(1)])
366 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(1)])
389 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(2)])
390 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(2)])
410 M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(3)])
411 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(3)])
434 str r0, [r12, #PMSAv8_RNR] @ PRSEL
437 str r5, [r12, #PMSAv8_RBAR_A(0)]
438 str r6, [r12, #PMSAv8_RLAR_A(0)]