Lines Matching refs:rp
42 #define checkuart(rp, rv, family_id, family) \ argument
44 ldr rp, =family_id ; \
46 cmp rp, rv ; \
48 ldreq rp, =UARTA_##family ; \
52 .macro addruart, rp, rv, tmp
53 adr \rp, 99f @ actual addr of 99f
54 ldr \rv, [\rp] @ linked addr is stored there
55 sub \rv, \rv, \rp @ offset between the two
56 ldr \rp, [\rp, #4] @ linked brcmstb_uart_config
57 sub \tmp, \rp, \rv @ actual brcmstb_uart_config
58 ldr \rp, [\tmp] @ Load brcmstb_uart_config
59 cmp \rp, #1 @ needs initialization?
66 ldr \rp, =ARM_CPU_PART_MASK
67 and \rv, \rv, \rp
68 ldr \rp, =ARM_CPU_PART_BRAHMA_B53 @ check for B53 CPU
69 cmp \rv, \rp
75 ldreq \rp, =SUN_TOP_CTRL_BASE_V7
78 10: ldrne \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA
79 ldr \rv, [\rp, #0] @ get register contents
84 20: checkuart(\rp, \rv, 0x33900000, 3390)
85 21: checkuart(\rp, \rv, 0x72500000, 7250)
86 22: checkuart(\rp, \rv, 0x72550000, 7255)
87 23: checkuart(\rp, \rv, 0x72600000, 7260)
88 24: checkuart(\rp, \rv, 0x72680000, 7268)
89 25: checkuart(\rp, \rv, 0x72710000, 7271)
90 26: checkuart(\rp, \rv, 0x72780000, 7278)
91 27: checkuart(\rp, \rv, 0x73640000, 7364)
92 28: checkuart(\rp, \rv, 0x73660000, 7366)
93 29: checkuart(\rp, \rv, 0x07437100, 74371)
94 30: checkuart(\rp, \rv, 0x74390000, 7439)
95 31: checkuart(\rp, \rv, 0x74450000, 7445)
98 90: mov \rp, #0
102 91: str \rp, [\tmp, #4] @ Store in brcmstb_uart_phys
103 cmp \rp, #0 @ Valid UART address?
105 str \rp, [\tmp, #8] @ Store 0 in brcmstb_uart_virt
107 92: and \rv, \rp, #0xffffff @ offset within 16MB section
118 100: ldr \rp, [\tmp, #4] @ Load brcmstb_uart_phys