Lines Matching +full:reset +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 interrupt-parent = <&lic>;
11 #address-cells = <1>;
12 #size-cells = <1>;
20 compatible = "nvidia,tegra30-pcie";
25 reg-names = "pads", "afi", "cs";
28 interrupt-names = "intr", "msi";
30 #interrupt-cells = <1>;
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
35 #address-cells = <3>;
36 #size-cells = <2>;
42 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
49 clock-names = "pex", "afi", "pll_e", "cml";
53 reset-names = "pex", "afi", "pcie_x";
58 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
60 bus-range = <0x00 0xff>;
63 #address-cells = <3>;
64 #size-cells = <2>;
67 nvidia,num-lanes = <2>;
72 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
74 bus-range = <0x00 0xff>;
77 #address-cells = <3>;
78 #size-cells = <2>;
81 nvidia,num-lanes = <2>;
86 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
88 bus-range = <0x00 0xff>;
91 #address-cells = <3>;
92 #size-cells = <2>;
95 nvidia,num-lanes = <2>;
100 compatible = "mmio-sram";
102 #address-cells = <1>;
103 #size-cells = <1>;
113 compatible = "nvidia,tegra30-host1x", "simple-bus";
119 reset-names = "host1x";
122 #address-cells = <1>;
123 #size-cells = <1>;
128 compatible = "nvidia,tegra30-mpe";
133 reset-names = "mpe";
139 compatible = "nvidia,tegra30-vi";
144 reset-names = "vi";
150 compatible = "nvidia,tegra30-epp";
155 reset-names = "epp";
161 compatible = "nvidia,tegra30-isp";
166 reset-names = "isp";
172 compatible = "nvidia,tegra30-gr2d";
177 reset-names = "2d";
183 compatible = "nvidia,tegra30-gr3d";
187 clock-names = "3d", "3d2";
190 reset-names = "3d", "3d2";
197 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
202 clock-names = "dc", "parent";
204 reset-names = "dc";
216 compatible = "nvidia,tegra30-dc";
221 clock-names = "dc", "parent";
223 reset-names = "dc";
235 compatible = "nvidia,tegra30-hdmi";
240 clock-names = "hdmi", "parent";
242 reset-names = "hdmi";
247 compatible = "nvidia,tegra30-tvo";
255 compatible = "nvidia,tegra30-dsi";
259 reset-names = "dsi";
265 compatible = "arm,cortex-a9-twd-timer";
267 interrupt-parent = <&intc>;
273 intc: interrupt-controller@50041000 {
274 compatible = "arm,cortex-a9-gic";
277 interrupt-controller;
278 #interrupt-cells = <3>;
279 interrupt-parent = <&intc>;
282 cache-controller@50043000 {
283 compatible = "arm,pl310-cache";
285 arm,data-latency = <6 6 2>;
286 arm,tag-latency = <5 5 2>;
287 cache-unified;
288 cache-level = <2>;
291 lic: interrupt-controller@60004000 {
292 compatible = "nvidia,tegra30-ictlr";
298 interrupt-controller;
299 #interrupt-cells = <3>;
300 interrupt-parent = <&intc>;
304 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
316 compatible = "nvidia,tegra30-car";
318 #clock-cells = <1>;
319 #reset-cells = <1>;
322 flow-controller@60007000 {
323 compatible = "nvidia,tegra30-flowctrl";
328 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
364 reset-names = "dma";
365 #dma-cells = <1>;
369 compatible = "nvidia,tegra30-ahb";
374 compatible = "nvidia,tegra30-actmon";
379 clock-names = "actmon", "emc";
381 reset-names = "actmon";
385 compatible = "nvidia,tegra30-gpio";
395 #gpio-cells = <2>;
396 gpio-controller;
397 #interrupt-cells = <2>;
398 interrupt-controller;
400 gpio-ranges = <&pinmux 0 0 248>;
405 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
409 0x6001c200 0x100 /* Post-processing Engine */
415 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
419 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
421 interrupt-names = "sync-token", "bsev", "sxe";
423 reset-names = "vde", "mc";
428 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
434 compatible = "nvidia,tegra30-pinmux";
443 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
445 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
448 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
450 reg-shift = <2>;
454 reset-names = "serial";
456 dma-names = "rx", "tx";
461 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
463 reg-shift = <2>;
467 reset-names = "serial";
469 dma-names = "rx", "tx";
474 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
476 reg-shift = <2>;
480 reset-names = "serial";
482 dma-names = "rx", "tx";
487 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
489 reg-shift = <2>;
493 reset-names = "serial";
495 dma-names = "rx", "tx";
500 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
502 reg-shift = <2>;
506 reset-names = "serial";
508 dma-names = "rx", "tx";
513 compatible = "nvidia,tegra30-gmi";
515 #address-cells = <2>;
516 #size-cells = <1>;
519 clock-names = "gmi";
521 reset-names = "gmi";
526 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
528 #pwm-cells = <2>;
531 reset-names = "pwm";
536 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
543 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
546 #address-cells = <1>;
547 #size-cells = <0>;
550 clock-names = "div-clk", "fast-clk";
552 reset-names = "i2c";
554 dma-names = "rx", "tx";
559 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
562 #address-cells = <1>;
563 #size-cells = <0>;
566 clock-names = "div-clk", "fast-clk";
568 reset-names = "i2c";
570 dma-names = "rx", "tx";
575 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
578 #address-cells = <1>;
579 #size-cells = <0>;
582 clock-names = "div-clk", "fast-clk";
584 reset-names = "i2c";
586 dma-names = "rx", "tx";
591 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
594 #address-cells = <1>;
595 #size-cells = <0>;
599 reset-names = "i2c";
600 clock-names = "div-clk", "fast-clk";
602 dma-names = "rx", "tx";
607 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
610 #address-cells = <1>;
611 #size-cells = <0>;
614 clock-names = "div-clk", "fast-clk";
616 reset-names = "i2c";
618 dma-names = "rx", "tx";
623 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
626 #address-cells = <1>;
627 #size-cells = <0>;
630 reset-names = "spi";
632 dma-names = "rx", "tx";
637 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
640 #address-cells = <1>;
641 #size-cells = <0>;
644 reset-names = "spi";
646 dma-names = "rx", "tx";
651 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
654 #address-cells = <1>;
655 #size-cells = <0>;
658 reset-names = "spi";
660 dma-names = "rx", "tx";
665 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
668 #address-cells = <1>;
669 #size-cells = <0>;
672 reset-names = "spi";
674 dma-names = "rx", "tx";
679 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
682 #address-cells = <1>;
683 #size-cells = <0>;
686 reset-names = "spi";
688 dma-names = "rx", "tx";
693 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
696 #address-cells = <1>;
697 #size-cells = <0>;
700 reset-names = "spi";
702 dma-names = "rx", "tx";
707 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
712 reset-names = "kbc";
717 compatible = "nvidia,tegra30-pmc";
720 clock-names = "pclk", "clk32k_in";
723 mc: memory-controller@7000f000 {
724 compatible = "nvidia,tegra30-mc";
727 clock-names = "mc";
731 #iommu-cells = <1>;
732 #reset-cells = <1>;
736 compatible = "nvidia,tegra30-efuse";
739 clock-names = "fuse";
741 reset-names = "fuse";
745 compatible = "nvidia,tegra30-hda";
751 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
755 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
760 compatible = "nvidia,tegra30-ahub";
766 clock-names = "d_audio", "apbif";
778 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
785 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
788 #address-cells = <1>;
789 #size-cells = <1>;
792 compatible = "nvidia,tegra30-i2s";
794 nvidia,ahub-cif-ids = <4 4>;
797 reset-names = "i2s";
802 compatible = "nvidia,tegra30-i2s";
804 nvidia,ahub-cif-ids = <5 5>;
807 reset-names = "i2s";
812 compatible = "nvidia,tegra30-i2s";
814 nvidia,ahub-cif-ids = <6 6>;
817 reset-names = "i2s";
822 compatible = "nvidia,tegra30-i2s";
824 nvidia,ahub-cif-ids = <7 7>;
827 reset-names = "i2s";
832 compatible = "nvidia,tegra30-i2s";
834 nvidia,ahub-cif-ids = <8 8>;
837 reset-names = "i2s";
843 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
848 reset-names = "sdhci";
853 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
858 reset-names = "sdhci";
863 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
868 reset-names = "sdhci";
873 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
878 reset-names = "sdhci";
883 compatible = "nvidia,tegra30-ehci", "usb-ehci";
889 reset-names = "usb";
890 nvidia,needs-double-reset;
895 phy1: usb-phy@7d000000 {
896 compatible = "nvidia,tegra30-usb-phy";
902 clock-names = "reg", "pll_u", "utmi-pads";
904 reset-names = "usb", "utmi-pads";
905 nvidia,hssync-start-delay = <9>;
906 nvidia,idle-wait-delay = <17>;
907 nvidia,elastic-limit = <16>;
908 nvidia,term-range-adj = <6>;
909 nvidia,xcvr-setup = <51>;
910 nvidia,xcvr-setup-use-fuses;
911 nvidia,xcvr-lsfslew = <1>;
912 nvidia,xcvr-lsrslew = <1>;
913 nvidia,xcvr-hsslew = <32>;
914 nvidia,hssquelch-level = <2>;
915 nvidia,hsdiscon-level = <5>;
916 nvidia,has-utmi-pad-registers;
921 compatible = "nvidia,tegra30-ehci", "usb-ehci";
927 reset-names = "usb";
932 phy2: usb-phy@7d004000 {
933 compatible = "nvidia,tegra30-usb-phy";
939 clock-names = "reg", "pll_u", "utmi-pads";
941 reset-names = "usb", "utmi-pads";
942 nvidia,hssync-start-delay = <9>;
943 nvidia,idle-wait-delay = <17>;
944 nvidia,elastic-limit = <16>;
945 nvidia,term-range-adj = <6>;
946 nvidia,xcvr-setup = <51>;
947 nvidia,xcvr-setup-use-fuses;
948 nvidia,xcvr-lsfslew = <2>;
949 nvidia,xcvr-lsrslew = <2>;
950 nvidia,xcvr-hsslew = <32>;
951 nvidia,hssquelch-level = <2>;
952 nvidia,hsdiscon-level = <5>;
957 compatible = "nvidia,tegra30-ehci", "usb-ehci";
963 reset-names = "usb";
968 phy3: usb-phy@7d008000 {
969 compatible = "nvidia,tegra30-usb-phy";
975 clock-names = "reg", "pll_u", "utmi-pads";
977 reset-names = "usb", "utmi-pads";
978 nvidia,hssync-start-delay = <0>;
979 nvidia,idle-wait-delay = <17>;
980 nvidia,elastic-limit = <16>;
981 nvidia,term-range-adj = <6>;
982 nvidia,xcvr-setup = <51>;
983 nvidia,xcvr-setup-use-fuses;
984 nvidia,xcvr-lsfslew = <2>;
985 nvidia,xcvr-lsrslew = <2>;
986 nvidia,xcvr-hsslew = <32>;
987 nvidia,hssquelch-level = <2>;
988 nvidia,hsdiscon-level = <5>;
993 #address-cells = <1>;
994 #size-cells = <0>;
998 compatible = "arm,cortex-a9";
1004 compatible = "arm,cortex-a9";
1010 compatible = "arm,cortex-a9";
1016 compatible = "arm,cortex-a9";
1022 compatible = "arm,cortex-a9-pmu";
1027 interrupt-affinity = <&{/cpus/cpu@0}>,