Lines Matching +full:reset +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 interrupt-parent = <&lic>;
11 #address-cells = <1>;
12 #size-cells = <1>;
20 compatible = "mmio-sram";
22 #address-cells = <1>;
23 #size-cells = <1>;
33 compatible = "nvidia,tegra20-host1x", "simple-bus";
39 reset-names = "host1x";
41 #address-cells = <1>;
42 #size-cells = <1>;
47 compatible = "nvidia,tegra20-mpe";
52 reset-names = "mpe";
56 compatible = "nvidia,tegra20-vi";
61 reset-names = "vi";
65 compatible = "nvidia,tegra20-epp";
70 reset-names = "epp";
74 compatible = "nvidia,tegra20-isp";
79 reset-names = "isp";
83 compatible = "nvidia,tegra20-gr2d";
88 reset-names = "2d";
92 compatible = "nvidia,tegra20-gr3d";
96 reset-names = "3d";
100 compatible = "nvidia,tegra20-dc";
105 clock-names = "dc", "parent";
107 reset-names = "dc";
117 compatible = "nvidia,tegra20-dc";
122 clock-names = "dc", "parent";
124 reset-names = "dc";
134 compatible = "nvidia,tegra20-hdmi";
139 clock-names = "hdmi", "parent";
141 reset-names = "hdmi";
146 compatible = "nvidia,tegra20-tvo";
154 compatible = "nvidia,tegra20-dsi";
158 reset-names = "dsi";
164 compatible = "arm,cortex-a9-twd-timer";
165 interrupt-parent = <&intc>;
172 intc: interrupt-controller@50041000 {
173 compatible = "arm,cortex-a9-gic";
176 interrupt-controller;
177 #interrupt-cells = <3>;
178 interrupt-parent = <&intc>;
181 cache-controller@50043000 {
182 compatible = "arm,pl310-cache";
184 arm,data-latency = <5 5 2>;
185 arm,tag-latency = <4 4 2>;
186 cache-unified;
187 cache-level = <2>;
190 lic: interrupt-controller@60004000 {
191 compatible = "nvidia,tegra20-ictlr";
196 interrupt-controller;
197 #interrupt-cells = <3>;
198 interrupt-parent = <&intc>;
202 compatible = "nvidia,tegra20-timer";
212 compatible = "nvidia,tegra20-car";
214 #clock-cells = <1>;
215 #reset-cells = <1>;
218 flow-controller@60007000 {
219 compatible = "nvidia,tegra20-flowctrl";
224 compatible = "nvidia,tegra20-apbdma";
244 reset-names = "dma";
245 #dma-cells = <1>;
249 compatible = "nvidia,tegra20-ahb";
254 compatible = "nvidia,tegra20-gpio";
263 #gpio-cells = <2>;
264 gpio-controller;
265 #interrupt-cells = <2>;
266 interrupt-controller;
268 gpio-ranges = <&pinmux 0 0 224>;
273 compatible = "nvidia,tegra20-vde";
277 0x6001c200 0x100 /* Post-processing Engine */
283 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
287 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
289 interrupt-names = "sync-token", "bsev", "sxe";
291 reset-names = "vde", "mc";
296 compatible = "nvidia,tegra20-apbmisc";
302 compatible = "nvidia,tegra20-pinmux";
303 reg = <0x70000014 0x10 /* Tri-state registers */
305 0x700000a0 0x14 /* Pull-up/down registers */
310 compatible = "nvidia,tegra20-das";
315 compatible = "nvidia,tegra20-ac97";
320 reset-names = "ac97";
322 dma-names = "rx", "tx";
327 compatible = "nvidia,tegra20-i2s";
332 reset-names = "i2s";
334 dma-names = "rx", "tx";
339 compatible = "nvidia,tegra20-i2s";
344 reset-names = "i2s";
346 dma-names = "rx", "tx";
354 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
355 * driver, the compatible is "nvidia,tegra20-hsuart".
358 compatible = "nvidia,tegra20-uart";
360 reg-shift = <2>;
364 reset-names = "serial";
366 dma-names = "rx", "tx";
371 compatible = "nvidia,tegra20-uart";
373 reg-shift = <2>;
377 reset-names = "serial";
379 dma-names = "rx", "tx";
384 compatible = "nvidia,tegra20-uart";
386 reg-shift = <2>;
390 reset-names = "serial";
392 dma-names = "rx", "tx";
397 compatible = "nvidia,tegra20-uart";
399 reg-shift = <2>;
403 reset-names = "serial";
405 dma-names = "rx", "tx";
410 compatible = "nvidia,tegra20-uart";
412 reg-shift = <2>;
416 reset-names = "serial";
418 dma-names = "rx", "tx";
422 nand-controller@70008000 {
423 compatible = "nvidia,tegra20-nand";
425 #address-cells = <1>;
426 #size-cells = <0>;
429 clock-names = "nand";
431 reset-names = "nand";
432 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
433 assigned-clock-rates = <150000000>;
438 compatible = "nvidia,tegra20-gmi";
440 #address-cells = <2>;
441 #size-cells = <1>;
444 clock-names = "gmi";
446 reset-names = "gmi";
451 compatible = "nvidia,tegra20-pwm";
453 #pwm-cells = <2>;
456 reset-names = "pwm";
461 compatible = "nvidia,tegra20-rtc";
468 compatible = "nvidia,tegra20-i2c";
471 #address-cells = <1>;
472 #size-cells = <0>;
475 clock-names = "div-clk", "fast-clk";
477 reset-names = "i2c";
479 dma-names = "rx", "tx";
484 compatible = "nvidia,tegra20-sflash";
487 #address-cells = <1>;
488 #size-cells = <0>;
491 reset-names = "spi";
493 dma-names = "rx", "tx";
498 compatible = "nvidia,tegra20-i2c";
501 #address-cells = <1>;
502 #size-cells = <0>;
505 clock-names = "div-clk", "fast-clk";
507 reset-names = "i2c";
509 dma-names = "rx", "tx";
514 compatible = "nvidia,tegra20-i2c";
517 #address-cells = <1>;
518 #size-cells = <0>;
521 clock-names = "div-clk", "fast-clk";
523 reset-names = "i2c";
525 dma-names = "rx", "tx";
530 compatible = "nvidia,tegra20-i2c-dvc";
533 #address-cells = <1>;
534 #size-cells = <0>;
537 clock-names = "div-clk", "fast-clk";
539 reset-names = "i2c";
541 dma-names = "rx", "tx";
546 compatible = "nvidia,tegra20-slink";
549 #address-cells = <1>;
550 #size-cells = <0>;
553 reset-names = "spi";
555 dma-names = "rx", "tx";
560 compatible = "nvidia,tegra20-slink";
563 #address-cells = <1>;
564 #size-cells = <0>;
567 reset-names = "spi";
569 dma-names = "rx", "tx";
574 compatible = "nvidia,tegra20-slink";
577 #address-cells = <1>;
578 #size-cells = <0>;
581 reset-names = "spi";
583 dma-names = "rx", "tx";
588 compatible = "nvidia,tegra20-slink";
591 #address-cells = <1>;
592 #size-cells = <0>;
595 reset-names = "spi";
597 dma-names = "rx", "tx";
602 compatible = "nvidia,tegra20-kbc";
607 reset-names = "kbc";
612 compatible = "nvidia,tegra20-pmc";
615 clock-names = "pclk", "clk32k_in";
618 mc: memory-controller@7000f000 {
619 compatible = "nvidia,tegra20-mc-gart";
623 clock-names = "mc";
625 #reset-cells = <1>;
626 #iommu-cells = <0>;
629 memory-controller@7000f400 {
630 compatible = "nvidia,tegra20-emc";
634 #address-cells = <1>;
635 #size-cells = <0>;
639 compatible = "nvidia,tegra20-efuse";
642 clock-names = "fuse";
644 reset-names = "fuse";
648 compatible = "nvidia,tegra20-pcie";
653 reg-names = "pads", "afi", "cs";
656 interrupt-names = "intr", "msi";
658 #interrupt-cells = <1>;
659 interrupt-map-mask = <0 0 0 0>;
660 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
662 bus-range = <0x00 0xff>;
663 #address-cells = <3>;
664 #size-cells = <2>;
669 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
675 clock-names = "pex", "afi", "pll_e";
679 reset-names = "pex", "afi", "pcie_x";
684 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
686 bus-range = <0x00 0xff>;
689 #address-cells = <3>;
690 #size-cells = <2>;
693 nvidia,num-lanes = <2>;
698 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
700 bus-range = <0x00 0xff>;
703 #address-cells = <3>;
704 #size-cells = <2>;
707 nvidia,num-lanes = <2>;
712 compatible = "nvidia,tegra20-ehci", "usb-ehci";
716 nvidia,has-legacy-mode;
719 reset-names = "usb";
720 nvidia,needs-double-reset;
725 phy1: usb-phy@c5000000 {
726 compatible = "nvidia,tegra20-usb-phy";
733 clock-names = "reg", "pll_u", "timer", "utmi-pads";
735 reset-names = "usb", "utmi-pads";
736 nvidia,has-legacy-mode;
737 nvidia,hssync-start-delay = <9>;
738 nvidia,idle-wait-delay = <17>;
739 nvidia,elastic-limit = <16>;
740 nvidia,term-range-adj = <6>;
741 nvidia,xcvr-setup = <9>;
742 nvidia,xcvr-lsfslew = <1>;
743 nvidia,xcvr-lsrslew = <1>;
744 nvidia,has-utmi-pad-registers;
749 compatible = "nvidia,tegra20-ehci", "usb-ehci";
755 reset-names = "usb";
760 phy2: usb-phy@c5004000 {
761 compatible = "nvidia,tegra20-usb-phy";
767 clock-names = "reg", "pll_u", "ulpi-link";
769 reset-names = "usb", "utmi-pads";
774 compatible = "nvidia,tegra20-ehci", "usb-ehci";
780 reset-names = "usb";
785 phy3: usb-phy@c5008000 {
786 compatible = "nvidia,tegra20-usb-phy";
793 clock-names = "reg", "pll_u", "timer", "utmi-pads";
795 reset-names = "usb", "utmi-pads";
796 nvidia,hssync-start-delay = <9>;
797 nvidia,idle-wait-delay = <17>;
798 nvidia,elastic-limit = <16>;
799 nvidia,term-range-adj = <6>;
800 nvidia,xcvr-setup = <9>;
801 nvidia,xcvr-lsfslew = <2>;
802 nvidia,xcvr-lsrslew = <2>;
807 compatible = "nvidia,tegra20-sdhci";
812 reset-names = "sdhci";
817 compatible = "nvidia,tegra20-sdhci";
822 reset-names = "sdhci";
827 compatible = "nvidia,tegra20-sdhci";
832 reset-names = "sdhci";
837 compatible = "nvidia,tegra20-sdhci";
842 reset-names = "sdhci";
847 #address-cells = <1>;
848 #size-cells = <0>;
852 compatible = "arm,cortex-a9";
858 compatible = "arm,cortex-a9";
864 compatible = "arm,cortex-a9-pmu";
867 interrupt-affinity = <&{/cpus/cpu@0}>,