Lines Matching +full:reset +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 interrupt-parent = <&lic>;
11 #address-cells = <1>;
12 #size-cells = <1>;
20 compatible = "nvidia,tegra114-host1x", "simple-bus";
26 reset-names = "host1x";
29 #address-cells = <1>;
30 #size-cells = <1>;
35 compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
40 reset-names = "2d";
46 compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
50 reset-names = "3d";
56 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
61 clock-names = "dc", "parent";
63 reset-names = "dc";
75 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
80 clock-names = "dc", "parent";
82 reset-names = "dc";
94 compatible = "nvidia,tegra114-hdmi";
99 clock-names = "hdmi", "parent";
101 reset-names = "hdmi";
106 compatible = "nvidia,tegra114-dsi";
111 clock-names = "dsi", "lp", "parent";
113 reset-names = "dsi";
114 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
117 #address-cells = <1>;
118 #size-cells = <0>;
122 compatible = "nvidia,tegra114-dsi";
127 clock-names = "dsi", "lp", "parent";
129 reset-names = "dsi";
130 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
133 #address-cells = <1>;
134 #size-cells = <0>;
138 gic: interrupt-controller@50041000 {
139 compatible = "arm,cortex-a15-gic";
140 #interrupt-cells = <3>;
141 interrupt-controller;
148 interrupt-parent = <&gic>;
151 lic: interrupt-controller@60004000 {
152 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
158 interrupt-controller;
159 #interrupt-cells = <3>;
160 interrupt-parent = <&gic>;
164 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
176 compatible = "nvidia,tegra114-car";
178 #clock-cells = <1>;
179 #reset-cells = <1>;
182 flow-controller@60007000 {
183 compatible = "nvidia,tegra114-flowctrl";
188 compatible = "nvidia,tegra114-apbdma";
224 reset-names = "dma";
225 #dma-cells = <1>;
229 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
234 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
244 #gpio-cells = <2>;
245 gpio-controller;
246 #interrupt-cells = <2>;
247 interrupt-controller;
249 gpio-ranges = <&pinmux 0 0 246>;
254 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
260 compatible = "nvidia,tegra114-pinmux";
269 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
271 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
274 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
276 reg-shift = <2>;
280 reset-names = "serial";
282 dma-names = "rx", "tx";
287 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
289 reg-shift = <2>;
293 reset-names = "serial";
295 dma-names = "rx", "tx";
300 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
302 reg-shift = <2>;
306 reset-names = "serial";
308 dma-names = "rx", "tx";
313 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
315 reg-shift = <2>;
319 reset-names = "serial";
321 dma-names = "rx", "tx";
326 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
328 #pwm-cells = <2>;
331 reset-names = "pwm";
336 compatible = "nvidia,tegra114-i2c";
339 #address-cells = <1>;
340 #size-cells = <0>;
342 clock-names = "div-clk";
344 reset-names = "i2c";
346 dma-names = "rx", "tx";
351 compatible = "nvidia,tegra114-i2c";
354 #address-cells = <1>;
355 #size-cells = <0>;
357 clock-names = "div-clk";
359 reset-names = "i2c";
361 dma-names = "rx", "tx";
366 compatible = "nvidia,tegra114-i2c";
369 #address-cells = <1>;
370 #size-cells = <0>;
372 clock-names = "div-clk";
374 reset-names = "i2c";
376 dma-names = "rx", "tx";
381 compatible = "nvidia,tegra114-i2c";
384 #address-cells = <1>;
385 #size-cells = <0>;
387 clock-names = "div-clk";
389 reset-names = "i2c";
391 dma-names = "rx", "tx";
396 compatible = "nvidia,tegra114-i2c";
399 #address-cells = <1>;
400 #size-cells = <0>;
402 clock-names = "div-clk";
404 reset-names = "i2c";
406 dma-names = "rx", "tx";
411 compatible = "nvidia,tegra114-spi";
414 #address-cells = <1>;
415 #size-cells = <0>;
417 clock-names = "spi";
419 reset-names = "spi";
421 dma-names = "rx", "tx";
426 compatible = "nvidia,tegra114-spi";
429 #address-cells = <1>;
430 #size-cells = <0>;
432 clock-names = "spi";
434 reset-names = "spi";
436 dma-names = "rx", "tx";
441 compatible = "nvidia,tegra114-spi";
444 #address-cells = <1>;
445 #size-cells = <0>;
447 clock-names = "spi";
449 reset-names = "spi";
451 dma-names = "rx", "tx";
456 compatible = "nvidia,tegra114-spi";
459 #address-cells = <1>;
460 #size-cells = <0>;
462 clock-names = "spi";
464 reset-names = "spi";
466 dma-names = "rx", "tx";
471 compatible = "nvidia,tegra114-spi";
474 #address-cells = <1>;
475 #size-cells = <0>;
477 clock-names = "spi";
479 reset-names = "spi";
481 dma-names = "rx", "tx";
486 compatible = "nvidia,tegra114-spi";
489 #address-cells = <1>;
490 #size-cells = <0>;
492 clock-names = "spi";
494 reset-names = "spi";
496 dma-names = "rx", "tx";
501 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
508 compatible = "nvidia,tegra114-kbc";
513 reset-names = "kbc";
518 compatible = "nvidia,tegra114-pmc";
521 clock-names = "pclk", "clk32k_in";
525 compatible = "nvidia,tegra114-efuse";
528 clock-names = "fuse";
530 reset-names = "fuse";
533 mc: memory-controller@70019000 {
534 compatible = "nvidia,tegra114-mc";
537 clock-names = "mc";
541 #iommu-cells = <1>;
545 compatible = "nvidia,tegra114-ahub";
552 clock-names = "d_audio", "apbif";
566 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
579 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
584 #address-cells = <1>;
585 #size-cells = <1>;
588 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
590 nvidia,ahub-cif-ids = <4 4>;
593 reset-names = "i2s";
598 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
600 nvidia,ahub-cif-ids = <5 5>;
603 reset-names = "i2s";
608 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
610 nvidia,ahub-cif-ids = <6 6>;
613 reset-names = "i2s";
618 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
620 nvidia,ahub-cif-ids = <7 7>;
623 reset-names = "i2s";
628 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
630 nvidia,ahub-cif-ids = <8 8>;
633 reset-names = "i2s";
639 compatible = "nvidia,tegra114-mipi";
642 #nvidia,mipi-calibrate-cells = <1>;
646 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
651 reset-names = "sdhci";
656 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
661 reset-names = "sdhci";
666 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
671 reset-names = "sdhci";
676 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
681 reset-names = "sdhci";
686 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
692 reset-names = "usb";
697 phy1: usb-phy@7d000000 {
698 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
704 clock-names = "reg", "pll_u", "utmi-pads";
706 reset-names = "usb", "utmi-pads";
707 nvidia,hssync-start-delay = <0>;
708 nvidia,idle-wait-delay = <17>;
709 nvidia,elastic-limit = <16>;
710 nvidia,term-range-adj = <6>;
711 nvidia,xcvr-setup = <9>;
712 nvidia,xcvr-lsfslew = <0>;
713 nvidia,xcvr-lsrslew = <3>;
714 nvidia,hssquelch-level = <2>;
715 nvidia,hsdiscon-level = <5>;
716 nvidia,xcvr-hsslew = <12>;
717 nvidia,has-utmi-pad-registers;
722 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
728 reset-names = "usb";
733 phy3: usb-phy@7d008000 {
734 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
740 clock-names = "reg", "pll_u", "utmi-pads";
742 reset-names = "usb", "utmi-pads";
743 nvidia,hssync-start-delay = <0>;
744 nvidia,idle-wait-delay = <17>;
745 nvidia,elastic-limit = <16>;
746 nvidia,term-range-adj = <6>;
747 nvidia,xcvr-setup = <9>;
748 nvidia,xcvr-lsfslew = <0>;
749 nvidia,xcvr-lsrslew = <3>;
750 nvidia,hssquelch-level = <2>;
751 nvidia,hsdiscon-level = <5>;
752 nvidia,xcvr-hsslew = <12>;
757 #address-cells = <1>;
758 #size-cells = <0>;
762 compatible = "arm,cortex-a15";
768 compatible = "arm,cortex-a15";
774 compatible = "arm,cortex-a15";
780 compatible = "arm,cortex-a15";
786 compatible = "arm,armv7-timer";
796 interrupt-parent = <&gic>;