Lines Matching +full:de_be0 +full:- +full:lcd0
2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
51 interrupt-parent = <&gic>;
52 #address-cells = <1>;
53 #size-cells = <1>;
56 #address-cells = <1>;
57 #size-cells = <1>;
60 simplefb_lcd: framebuffer-lcd0 {
61 compatible = "allwinner,simple-framebuffer",
62 "simple-framebuffer";
63 allwinner,pipeline = "de_be0-lcd0";
71 de: display-engine {
78 compatible = "arm,armv7-timer";
83 clock-frequency = <24000000>;
84 arm,cpu-registers-not-fw-configured;
88 enable-method = "allwinner,sun8i-a23";
89 #address-cells = <1>;
90 #size-cells = <0>;
93 compatible = "arm,cortex-a7";
99 compatible = "arm,cortex-a7";
106 #address-cells = <1>;
107 #size-cells = <1>;
111 #clock-cells = <0>;
112 compatible = "fixed-clock";
113 clock-frequency = <24000000>;
114 clock-accuracy = <50000>;
115 clock-output-names = "osc24M";
119 #clock-cells = <0>;
120 compatible = "fixed-clock";
121 clock-frequency = <32768>;
122 clock-accuracy = <50000>;
123 clock-output-names = "ext-osc32k";
128 compatible = "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <1>;
133 system-control@1c00000 {
134 compatible = "allwinner,sun8i-a23-system-control";
136 #address-cells = <1>;
137 #size-cells = <1>;
141 compatible = "mmio-sram";
143 #address-cells = <1>;
144 #size-cells = <1>;
147 ve_sram: sram-section@0 {
148 compatible = "allwinner,sun8i-a23-sram-c1",
149 "allwinner,sun4i-a10-sram-c1";
155 dma: dma-controller@1c02000 {
156 compatible = "allwinner,sun8i-a23-dma";
161 #dma-cells = <1>;
164 nfc: nand-controller@1c03000 {
165 compatible = "allwinner,sun8i-a23-nand-controller";
169 clock-names = "ahb", "mod";
171 reset-names = "ahb";
173 dma-names = "rxtx";
174 pinctrl-names = "default";
175 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
177 #address-cells = <1>;
178 #size-cells = <0>;
181 tcon0: lcd-controller@1c0c000 {
187 clock-names = "ahb",
188 "tcon-ch0";
189 clock-output-names = "tcon-pixel-clock";
190 #clock-cells = <0>;
192 reset-names = "lcd";
196 #address-cells = <1>;
197 #size-cells = <0>;
203 remote-endpoint = <&drc0_out_tcon0>;
214 compatible = "allwinner,sun7i-a20-mmc";
220 clock-names = "ahb",
225 reset-names = "ahb";
227 pinctrl-names = "default";
228 pinctrl-0 = <&mmc0_pins>;
230 #address-cells = <1>;
231 #size-cells = <0>;
235 compatible = "allwinner,sun7i-a20-mmc";
241 clock-names = "ahb",
246 reset-names = "ahb";
249 #address-cells = <1>;
250 #size-cells = <0>;
254 compatible = "allwinner,sun7i-a20-mmc";
260 clock-names = "ahb",
265 reset-names = "ahb";
268 #address-cells = <1>;
269 #size-cells = <0>;
278 interrupt-names = "mc";
280 phy-names = "usb";
293 clock-names = "usb0_phy",
297 reset-names = "usb0_reset",
300 #phy-cells = <1>;
304 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
310 phy-names = "usb";
315 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
321 phy-names = "usb";
328 clock-names = "hosc", "losc";
329 #clock-cells = <1>;
330 #reset-cells = <1>;
338 clock-names = "apb", "hosc", "losc";
339 gpio-controller;
340 interrupt-controller;
341 #interrupt-cells = <3>;
342 #gpio-cells = <3>;
344 i2c0_pins: i2c0-pins {
349 i2c1_pins: i2c1-pins {
354 i2c2_pins: i2c2-pins {
359 lcd_rgb666_pins: lcd-rgb666-pins {
364 function = "lcd0";
367 mmc0_pins: mmc0-pins {
371 drive-strength = <30>;
372 bias-pull-up;
375 mmc1_pg_pins: mmc1-pg-pins {
379 drive-strength = <30>;
380 bias-pull-up;
383 mmc2_8bit_pins: mmc2-8bit-pins {
389 drive-strength = <30>;
390 bias-pull-up;
393 nand_pins: nand-pins {
400 nand_cs0_pin: nand-cs0-pin {
403 bias-pull-up;
406 nand_cs1_pin: nand-cs1-pin {
409 bias-pull-up;
412 nand_rb0_pin: nand-rb0-pin {
415 bias-pull-up;
418 nand_rb1_pin: nand-rb1-pin {
421 bias-pull-up;
424 pwm0_pin: pwm0-pin {
429 uart0_pf_pins: uart0-pf-pins {
434 uart1_pg_pins: uart1-pg-pins {
439 uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
446 compatible = "allwinner,sun8i-a23-timer";
454 compatible = "allwinner,sun6i-a31-wdt";
461 compatible = "allwinner,sun7i-a20-pwm";
464 #pwm-cells = <3>;
469 compatible = "allwinner,sun4i-a10-lradc-keys";
476 compatible = "snps,dw-apb-uart";
479 reg-shift = <2>;
480 reg-io-width = <4>;
484 dma-names = "rx", "tx";
489 compatible = "snps,dw-apb-uart";
492 reg-shift = <2>;
493 reg-io-width = <4>;
497 dma-names = "rx", "tx";
502 compatible = "snps,dw-apb-uart";
505 reg-shift = <2>;
506 reg-io-width = <4>;
510 dma-names = "rx", "tx";
515 compatible = "snps,dw-apb-uart";
518 reg-shift = <2>;
519 reg-io-width = <4>;
523 dma-names = "rx", "tx";
528 compatible = "snps,dw-apb-uart";
531 reg-shift = <2>;
532 reg-io-width = <4>;
536 dma-names = "rx", "tx";
541 compatible = "allwinner,sun6i-a31-i2c";
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c0_pins>;
549 #address-cells = <1>;
550 #size-cells = <0>;
554 compatible = "allwinner,sun6i-a31-i2c";
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c1_pins>;
562 #address-cells = <1>;
563 #size-cells = <0>;
567 compatible = "allwinner,sun6i-a31-i2c";
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c2_pins>;
575 #address-cells = <1>;
576 #size-cells = <0>;
580 compatible = "allwinner,sun8i-a23-mali",
581 "allwinner,sun7i-a20-mali", "arm,mali-400";
590 interrupt-names = "gp",
598 clock-names = "bus", "core";
600 #cooling-cells = <2>;
602 assigned-clocks = <&ccu CLK_GPU>;
603 assigned-clock-rates = <384000000>;
606 gic: interrupt-controller@1c81000 {
607 compatible = "arm,gic-400";
612 interrupt-controller;
613 #interrupt-cells = <3>;
617 fe0: display-frontend@1e00000 {
623 clock-names = "ahb", "mod",
628 #address-cells = <1>;
629 #size-cells = <0>;
635 remote-endpoint = <&be0_in_fe0>;
641 be0: display-backend@1e60000 {
647 clock-names = "ahb", "mod",
652 #address-cells = <1>;
653 #size-cells = <0>;
659 remote-endpoint = <&fe0_out_be0>;
667 remote-endpoint = <&drc0_in_be0>;
679 clock-names = "ahb", "mod", "ram";
682 assigned-clocks = <&ccu CLK_DRC>;
683 assigned-clock-rates = <300000000>;
686 #address-cells = <1>;
687 #size-cells = <0>;
693 remote-endpoint = <&be0_out_drc0>;
701 remote-endpoint = <&tcon0_in_drc0>;
708 compatible = "allwinner,sun8i-a23-rtc";
712 clock-output-names = "osc32k", "osc32k-out";
714 #clock-cells = <1>;
717 nmi_intc: interrupt-controller@1f00c00 {
718 compatible = "allwinner,sun6i-a31-r-intc";
719 interrupt-controller;
720 #interrupt-cells = <2>;
726 compatible = "allwinner,sun8i-a23-prcm";
730 compatible = "fixed-factor-clock";
731 #clock-cells = <0>;
732 clock-div = <1>;
733 clock-mult = <1>;
735 clock-output-names = "ar100";
739 compatible = "fixed-factor-clock";
740 #clock-cells = <0>;
741 clock-div = <1>;
742 clock-mult = <1>;
744 clock-output-names = "ahb0";
748 compatible = "allwinner,sun8i-a23-apb0-clk";
749 #clock-cells = <0>;
751 clock-output-names = "apb0";
755 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
756 #clock-cells = <1>;
758 clock-output-names = "apb0_pio", "apb0_timer",
764 compatible = "allwinner,sun6i-a31-clock-reset";
765 #reset-cells = <1>;
768 codec_analog: codec-analog {
769 compatible = "allwinner,sun8i-a23-codec-analog";
774 compatible = "allwinner,sun8i-a23-cpuconfig";
779 compatible = "snps,dw-apb-uart";
782 reg-shift = <2>;
783 reg-io-width = <4>;
790 compatible = "allwinner,sun8i-a23-i2c",
791 "allwinner,sun6i-a31-i2c";
794 pinctrl-names = "default";
795 pinctrl-0 = <&r_i2c_pins>;
799 #address-cells = <1>;
800 #size-cells = <0>;
804 compatible = "allwinner,sun8i-a23-r-pinctrl";
808 clock-names = "apb", "hosc", "losc";
810 gpio-controller;
811 interrupt-controller;
812 #interrupt-cells = <3>;
813 #gpio-cells = <3>;
815 r_i2c_pins: r-i2c-pins {
818 bias-pull-up;
821 r_rsb_pins: r-rsb-pins {
824 drive-strength = <20>;
825 bias-pull-up;
828 r_uart_pins_a: r-uart-pins {
835 compatible = "allwinner,sun8i-a23-rsb";
839 clock-frequency = <3000000>;
841 pinctrl-names = "default";
842 pinctrl-0 = <&r_rsb_pins>;
844 #address-cells = <1>;
845 #size-cells = <0>;