Lines Matching +full:sun4i +full:- +full:a10 +full:- +full:ic
2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
56 #size-cells = <0>;
60 compatible = "arm,cortex-a8";
67 #address-cells = <1>;
68 #size-cells = <1>;
71 framebuffer-lcd0 {
72 compatible = "allwinner,simple-framebuffer",
73 "simple-framebuffer";
74 allwinner,pipeline = "de_be0-lcd0";
80 framebuffer-lcd0-tve0 {
81 compatible = "allwinner,simple-framebuffer",
82 "simple-framebuffer";
83 allwinner,pipeline = "de_be0-lcd0-tve0";
92 #address-cells = <1>;
93 #size-cells = <1>;
96 osc24M: clk-24M {
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 clock-frequency = <24000000>;
100 clock-output-names = "osc24M";
103 osc32k: clk-32k {
104 #clock-cells = <0>;
105 compatible = "fixed-clock";
106 clock-frequency = <32768>;
107 clock-output-names = "osc32k";
111 reserved-memory {
112 #address-cells = <1>;
113 #size-cells = <1>;
117 default-pool {
118 compatible = "shared-dma-pool";
120 alloc-ranges = <0x4a000000 0x6000000>;
122 linux,cma-default;
127 compatible = "simple-bus";
128 #address-cells = <1>;
129 #size-cells = <1>;
130 dma-ranges;
133 system-control@1c00000 {
134 compatible = "allwinner,sun5i-a13-system-control";
136 #address-cells = <1>;
137 #size-cells = <1>;
141 compatible = "mmio-sram";
143 #address-cells = <1>;
144 #size-cells = <1>;
147 emac_sram: sram-section@8000 {
148 compatible = "allwinner,sun5i-a13-sram-a3-a4",
149 "allwinner,sun4i-a10-sram-a3-a4";
156 compatible = "mmio-sram";
158 #address-cells = <1>;
159 #size-cells = <1>;
162 otg_sram: sram-section@0 {
163 compatible = "allwinner,sun5i-a13-sram-d",
164 "allwinner,sun4i-a10-sram-d";
171 compatible = "mmio-sram";
173 #address-cells = <1>;
174 #size-cells = <1>;
177 ve_sram: sram-section@0 {
178 compatible = "allwinner,sun5i-a13-sram-c1",
179 "allwinner,sun4i-a10-sram-c1";
185 mbus: dram-controller@1c01000 {
186 compatible = "allwinner,sun5i-a13-mbus";
189 dma-ranges = <0x00000000 0x40000000 0x20000000>;
190 #interconnect-cells = <1>;
193 dma: dma-controller@1c02000 {
194 compatible = "allwinner,sun4i-a10-dma";
198 #dma-cells = <2>;
201 nfc: nand-controller@1c03000 {
202 compatible = "allwinner,sun4i-a10-nand";
206 clock-names = "ahb", "mod";
208 dma-names = "rxtx";
210 #address-cells = <1>;
211 #size-cells = <0>;
215 compatible = "allwinner,sun4i-a10-spi";
219 clock-names = "ahb", "mod";
222 dma-names = "rx", "tx";
224 #address-cells = <1>;
225 #size-cells = <0>;
229 compatible = "allwinner,sun4i-a10-spi";
233 clock-names = "ahb", "mod";
236 dma-names = "rx", "tx";
238 #address-cells = <1>;
239 #size-cells = <0>;
242 tve0: tv-encoder@1c0a000 {
243 compatible = "allwinner,sun4i-a10-tv-encoder";
252 remote-endpoint = <&tcon0_out_tve0>;
258 compatible = "allwinner,sun4i-a10-emac";
267 compatible = "allwinner,sun4i-a10-mdio";
270 #address-cells = <1>;
271 #size-cells = <0>;
274 tcon0: lcd-controller@1c0c000 {
275 compatible = "allwinner,sun5i-a13-tcon";
279 reset-names = "lcd";
283 clock-names = "ahb",
284 "tcon-ch0",
285 "tcon-ch1";
286 clock-output-names = "tcon-pixel-clock";
287 #clock-cells = <0>;
291 #address-cells = <1>;
292 #size-cells = <0>;
298 remote-endpoint = <&be0_out_tcon0>;
303 #address-cells = <1>;
304 #size-cells = <0>;
309 remote-endpoint = <&tve0_in_tcon0>;
310 allwinner,tcon-channel = <1>;
316 video-codec@1c0e000 {
317 compatible = "allwinner,sun5i-a13-video-engine";
321 clock-names = "ahb", "mod", "ram";
328 compatible = "allwinner,sun5i-a13-mmc";
331 clock-names = "ahb", "mmc";
333 pinctrl-names = "default";
334 pinctrl-0 = <&mmc0_pins>;
336 #address-cells = <1>;
337 #size-cells = <0>;
341 compatible = "allwinner,sun5i-a13-mmc";
344 clock-names = "ahb", "mmc";
347 #address-cells = <1>;
348 #size-cells = <0>;
352 compatible = "allwinner,sun5i-a13-mmc";
355 clock-names = "ahb", "mmc";
358 #address-cells = <1>;
359 #size-cells = <0>;
363 compatible = "allwinner,sun4i-a10-musb";
367 interrupt-names = "mc";
369 phy-names = "usb";
377 #phy-cells = <1>;
378 compatible = "allwinner,sun5i-a13-usb-phy";
380 reg-names = "phy_ctrl", "pmu1";
382 clock-names = "usb_phy";
384 reset-names = "usb0_reset", "usb1_reset";
389 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
394 phy-names = "usb";
399 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
404 phy-names = "usb";
408 crypto: crypto-engine@1c15000 {
409 compatible = "allwinner,sun5i-a13-crypto",
410 "allwinner,sun4i-a10-crypto";
414 clock-names = "ahb", "mod";
418 compatible = "allwinner,sun4i-a10-spi";
422 clock-names = "ahb", "mod";
425 dma-names = "rx", "tx";
427 #address-cells = <1>;
428 #size-cells = <0>;
434 clock-names = "hosc", "losc";
435 #clock-cells = <1>;
436 #reset-cells = <1>;
439 intc: interrupt-controller@1c20400 {
440 compatible = "allwinner,sun4i-a10-ic";
442 interrupt-controller;
443 #interrupt-cells = <1>;
450 clock-names = "apb", "hosc", "losc";
451 gpio-controller;
452 interrupt-controller;
453 #interrupt-cells = <3>;
454 #gpio-cells = <3>;
456 emac_pd_pins: emac-pd-pins {
465 i2c0_pins: i2c0-pins {
470 i2c1_pins: i2c1-pins {
475 i2c2_pins: i2c2-pins {
480 ir0_rx_pin: ir0-rx-pin {
485 lcd_rgb565_pins: lcd-rgb565-pins {
493 lcd_rgb666_pins: lcd-rgb666-pins {
501 mmc0_pins: mmc0-pins {
505 drive-strength = <30>;
506 bias-pull-up;
509 mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
513 drive-strength = <30>;
514 bias-pull-up;
517 mmc2_8bit_pins: mmc2-8bit-pins {
522 drive-strength = <30>;
523 bias-pull-up;
526 nand_pins: nand-pins {
534 nand_cs0_pin: nand-cs0-pin {
539 nand_rb0_pin: nand-rb0-pin {
544 pwm0_pin: pwm0-pin {
549 spi2_pe_pins: spi2-pe-pins {
554 spi2_cs0_pe_pin: spi2-cs0-pe-pin {
559 uart1_pe_pins: uart1-pe-pins {
564 uart1_pg_pins: uart1-pg-pins {
569 uart2_pd_pins: uart2-pd-pins {
574 uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
579 uart3_pg_pins: uart3-pg-pins {
584 uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
591 compatible = "allwinner,sun4i-a10-timer";
603 compatible = "allwinner,sun4i-a10-wdt";
610 compatible = "allwinner,sun4i-a10-ir";
612 clock-names = "apb", "ir";
619 compatible = "allwinner,sun4i-a10-lradc-keys";
626 #sound-dai-cells = <0>;
627 compatible = "allwinner,sun4i-a10-codec";
631 clock-names = "apb", "codec";
634 dma-names = "rx", "tx";
639 compatible = "allwinner,sun4i-a10-sid";
644 compatible = "allwinner,sun5i-a13-ts";
647 #thermal-sensor-cells = <0>;
651 compatible = "snps,dw-apb-uart";
654 reg-shift = <2>;
655 reg-io-width = <4>;
661 compatible = "snps,dw-apb-uart";
664 reg-shift = <2>;
665 reg-io-width = <4>;
671 compatible = "snps,dw-apb-uart";
674 reg-shift = <2>;
675 reg-io-width = <4>;
681 compatible = "snps,dw-apb-uart";
684 reg-shift = <2>;
685 reg-io-width = <4>;
691 compatible = "allwinner,sun4i-a10-i2c";
695 pinctrl-names = "default";
696 pinctrl-0 = <&i2c0_pins>;
698 #address-cells = <1>;
699 #size-cells = <0>;
703 compatible = "allwinner,sun4i-a10-i2c";
707 pinctrl-names = "default";
708 pinctrl-0 = <&i2c1_pins>;
710 #address-cells = <1>;
711 #size-cells = <0>;
715 compatible = "allwinner,sun4i-a10-i2c";
719 pinctrl-names = "default";
720 pinctrl-0 = <&i2c2_pins>;
722 #address-cells = <1>;
723 #size-cells = <0>;
727 compatible = "allwinner,sun5i-a13-hstimer";
733 fe0: display-frontend@1e00000 {
734 compatible = "allwinner,sun5i-a13-display-frontend";
739 clock-names = "ahb", "mod",
743 interconnect-names = "dma-mem";
747 #address-cells = <1>;
748 #size-cells = <0>;
754 remote-endpoint = <&be0_in_fe0>;
760 be0: display-backend@1e60000 {
761 compatible = "allwinner,sun5i-a13-display-backend";
766 clock-names = "ahb", "mod",
770 interconnect-names = "dma-mem";
773 assigned-clocks = <&ccu CLK_DE_BE>;
774 assigned-clock-rates = <300000000>;
777 #address-cells = <1>;
778 #size-cells = <0>;
784 remote-endpoint = <&fe0_out_be0>;
792 remote-endpoint = <&tcon0_in_be0>;