Lines Matching refs:gcc
5 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
238 clocks = <&gcc GSBI2_H_CLK>;
252 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
262 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
276 clocks = <&gcc GSBI4_H_CLK>;
290 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
300 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
313 clocks = <&gcc GSBI5_H_CLK>;
327 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
337 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
350 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
364 clocks = <&gcc GSBI7_H_CLK>;
376 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
386 clocks = <&gcc SATA_PHY_CFG_CLK>;
399 clocks = <&gcc SFAB_SATA_S_H_CLK>,
400 <&gcc SATA_H_CLK>,
401 <&gcc SATA_A_CLK>,
402 <&gcc SATA_RXOOB_CLK>,
403 <&gcc SATA_PMALIVE_CLK>;
407 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
421 gcc: clock-controller@900000 { label
422 compatible = "qcom,gcc-ipq8064";
466 clocks = <&gcc PCIE_A_CLK>,
467 <&gcc PCIE_H_CLK>,
468 <&gcc PCIE_PHY_CLK>,
469 <&gcc PCIE_AUX_CLK>,
470 <&gcc PCIE_ALT_REF_CLK>;
473 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
476 resets = <&gcc PCIE_ACLK_RESET>,
477 <&gcc PCIE_HCLK_RESET>,
478 <&gcc PCIE_POR_RESET>,
479 <&gcc PCIE_PCI_RESET>,
480 <&gcc PCIE_PHY_RESET>,
481 <&gcc PCIE_EXT_RESET>;
517 clocks = <&gcc PCIE_1_A_CLK>,
518 <&gcc PCIE_1_H_CLK>,
519 <&gcc PCIE_1_PHY_CLK>,
520 <&gcc PCIE_1_AUX_CLK>,
521 <&gcc PCIE_1_ALT_REF_CLK>;
524 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
527 resets = <&gcc PCIE_1_ACLK_RESET>,
528 <&gcc PCIE_1_HCLK_RESET>,
529 <&gcc PCIE_1_POR_RESET>,
530 <&gcc PCIE_1_PCI_RESET>,
531 <&gcc PCIE_1_PHY_RESET>,
532 <&gcc PCIE_1_EXT_RESET>;
568 clocks = <&gcc PCIE_2_A_CLK>,
569 <&gcc PCIE_2_H_CLK>,
570 <&gcc PCIE_2_PHY_CLK>,
571 <&gcc PCIE_2_AUX_CLK>,
572 <&gcc PCIE_2_ALT_REF_CLK>;
575 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
578 resets = <&gcc PCIE_2_ACLK_RESET>,
579 <&gcc PCIE_2_HCLK_RESET>,
580 <&gcc PCIE_2_POR_RESET>,
581 <&gcc PCIE_2_PCI_RESET>,
582 <&gcc PCIE_2_PHY_RESET>,
583 <&gcc PCIE_2_EXT_RESET>;
605 clocks = <&gcc SDC1_H_CLK>;
615 clocks = <&gcc SDC3_H_CLK>;
634 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
654 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;