Lines Matching refs:gcc
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
108 thermal-sensors = <&gcc 7>;
129 thermal-sensors = <&gcc 8>;
150 thermal-sensors = <&gcc 9>;
171 thermal-sensors = <&gcc 10>;
441 clocks = <&gcc GSBI1_H_CLK>;
454 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
466 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
480 clocks = <&gcc GSBI2_H_CLK>;
495 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
508 clocks = <&gcc GSBI3_H_CLK>;
520 clocks = <&gcc GSBI3_QUP_CLK>,
521 <&gcc GSBI3_H_CLK>;
534 clocks = <&gcc GSBI4_H_CLK>;
547 clocks = <&gcc GSBI4_QUP_CLK>,
548 <&gcc GSBI4_H_CLK>;
559 clocks = <&gcc GSBI5_H_CLK>;
570 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
582 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
595 clocks = <&gcc GSBI6_H_CLK>;
606 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
618 clocks = <&gcc GSBI6_QUP_CLK>,
619 <&gcc GSBI6_H_CLK>;
630 clocks = <&gcc GSBI7_H_CLK>;
642 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
654 clocks = <&gcc GSBI7_QUP_CLK>,
655 <&gcc GSBI7_H_CLK>;
664 clocks = <&gcc PRNG_CLK>;
822 gcc: clock-controller@900000 { label
823 compatible = "qcom,gcc-apq8064";
926 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
928 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
930 resets = <&gcc USB_HS1_RESET>;
957 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
959 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
961 resets = <&gcc USB_HS3_RESET>;
988 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
990 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
992 resets = <&gcc USB_HS4_RESET>;
1019 clocks = <&gcc SATA_PHY_CFG_CLK>;
1030 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1031 <&gcc SATA_H_CLK>,
1032 <&gcc SATA_A_CLK>,
1033 <&gcc SATA_RXOOB_CLK>,
1034 <&gcc SATA_PMALIVE_CLK>;
1041 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1042 <&gcc SATA_PMALIVE_CLK>;
1055 clocks = <&gcc SDC1_H_CLK>;
1065 clocks = <&gcc SDC3_H_CLK>;
1075 clocks = <&gcc SDC4_H_CLK>;
1095 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1113 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1131 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1399 clocks = <&gcc PCIE_A_CLK>,
1400 <&gcc PCIE_H_CLK>,
1401 <&gcc PCIE_PHY_REF_CLK>;
1403 resets = <&gcc PCIE_ACLK_RESET>,
1404 <&gcc PCIE_HCLK_RESET>,
1405 <&gcc PCIE_POR_RESET>,
1406 <&gcc PCIE_PCI_RESET>,
1407 <&gcc PCIE_PHY_RESET>;