Lines Matching +full:clock +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0-only
8 #address-cells = <1>;
9 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm1176jz-s";
18 cpu-clock = <&arm_clk>, "cpu";
19 d-cache-line-size = <32>;
20 d-cache-size = <32768>;
21 i-cache-line-size = <32>;
22 i-cache-size = <32768>;
27 #address-cells = <1>;
28 #size-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
35 compatible = "picochip,pc3x3-clk-gate";
37 tzprot_clk: clock@0 {
38 compatible = "picochip,pc3x3-gated-clk";
39 clock-outputs = "bus";
40 picochip,clk-disable-bit = <0>;
41 clock-frequency = <200000000>;
42 ref-clock = <&ref_clk>, "ref";
45 spi_clk: clock@1 {
46 compatible = "picochip,pc3x3-gated-clk";
47 clock-outputs = "bus";
48 picochip,clk-disable-bit = <1>;
49 clock-frequency = <200000000>;
50 ref-clock = <&ref_clk>, "ref";
53 dmac0_clk: clock@2 {
54 compatible = "picochip,pc3x3-gated-clk";
55 clock-outputs = "bus";
56 picochip,clk-disable-bit = <2>;
57 clock-frequency = <200000000>;
58 ref-clock = <&ref_clk>, "ref";
61 dmac1_clk: clock@3 {
62 compatible = "picochip,pc3x3-gated-clk";
63 clock-outputs = "bus";
64 picochip,clk-disable-bit = <3>;
65 clock-frequency = <200000000>;
66 ref-clock = <&ref_clk>, "ref";
69 ebi_clk: clock@4 {
70 compatible = "picochip,pc3x3-gated-clk";
71 clock-outputs = "bus";
72 picochip,clk-disable-bit = <4>;
73 clock-frequency = <200000000>;
74 ref-clock = <&ref_clk>, "ref";
77 ipsec_clk: clock@5 {
78 compatible = "picochip,pc3x3-gated-clk";
79 clock-outputs = "bus";
80 picochip,clk-disable-bit = <5>;
81 clock-frequency = <200000000>;
82 ref-clock = <&ref_clk>, "ref";
85 l2_clk: clock@6 {
86 compatible = "picochip,pc3x3-gated-clk";
87 clock-outputs = "bus";
88 picochip,clk-disable-bit = <6>;
89 clock-frequency = <200000000>;
90 ref-clock = <&ref_clk>, "ref";
93 trng_clk: clock@7 {
94 compatible = "picochip,pc3x3-gated-clk";
95 clock-outputs = "bus";
96 picochip,clk-disable-bit = <7>;
97 clock-frequency = <200000000>;
98 ref-clock = <&ref_clk>, "ref";
101 fuse_clk: clock@8 {
102 compatible = "picochip,pc3x3-gated-clk";
103 clock-outputs = "bus";
104 picochip,clk-disable-bit = <8>;
105 clock-frequency = <200000000>;
106 ref-clock = <&ref_clk>, "ref";
109 otp_clk: clock@9 {
110 compatible = "picochip,pc3x3-gated-clk";
111 clock-outputs = "bus";
112 picochip,clk-disable-bit = <9>;
113 clock-frequency = <200000000>;
114 ref-clock = <&ref_clk>, "ref";
118 arm_clk: clock@11 {
119 compatible = "picochip,pc3x3-pll";
121 picochip,min-freq = <140000000>;
122 picochip,max-freq = <700000000>;
123 ref-clock = <&ref_clk>, "ref";
124 clock-outputs = "cpu";
127 pclk: clock@12 {
128 compatible = "fixed-clock";
129 clock-outputs = "bus", "pclk";
130 clock-frequency = <200000000>;
131 ref-clock = <&ref_clk>, "ref";
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
144 interrupt-parent = <&vic0>;
149 compatible = "snps,dw-dmac";
151 interrupt-parent = <&vic0>;
156 compatible = "snps,dw-dmac";
158 interrupt-parent = <&vic0>;
162 vic0: interrupt-controller@60000 {
163 compatible = "arm,pl192-vic";
164 interrupt-controller;
166 #interrupt-cells = <1>;
169 vic1: interrupt-controller@64000 {
170 compatible = "arm,pl192-vic";
171 interrupt-controller;
173 #interrupt-cells = <1>;
176 fuse: picoxcell-fuse@80000 {
177 compatible = "picoxcell,fuse-pc3x3";
181 ssi: picoxcell-spi@90000 {
184 interrupt-parent = <&vic0>;
189 compatible = "picochip,spacc-ipsec";
191 interrupt-parent = <&vic0>;
193 ref-clock = <&ipsec_clk>, "ref";
197 compatible = "picochip,spacc-srtp";
199 interrupt-parent = <&vic0>;
204 compatible = "picochip,spacc-l2";
206 interrupt-parent = <&vic0>;
208 ref-clock = <&l2_clk>, "ref";
212 compatible = "simple-bus";
213 #address-cells = <1>;
214 #size-cells = <1>;
218 compatible = "picochip,pc3x2-rtc";
219 clock-freq = <200000000>;
221 interrupt-parent = <&vic0>;
226 compatible = "picochip,pc3x2-timer";
227 interrupt-parent = <&vic0>;
229 clock-freq = <200000000>;
234 compatible = "picochip,pc3x2-timer";
235 interrupt-parent = <&vic0>;
237 clock-freq = <200000000>;
242 compatible = "snps,dw-apb-gpio";
244 #address-cells = <1>;
245 #size-cells = <0>;
246 reg-io-width = <4>;
248 banka: gpio-controller@0 {
249 compatible = "snps,dw-apb-gpio-bank";
250 gpio-controller;
251 #gpio-cells = <2>;
252 gpio-generic,nr-gpio = <8>;
254 regoffset-dat = <0x50>;
255 regoffset-set = <0x00>;
256 regoffset-dirout = <0x04>;
259 bankb: gpio-controller@1 {
260 compatible = "snps,dw-apb-gpio-bank";
261 gpio-controller;
262 #gpio-cells = <2>;
263 gpio-generic,nr-gpio = <16>;
265 regoffset-dat = <0x54>;
266 regoffset-set = <0x0c>;
267 regoffset-dirout = <0x10>;
270 bankd: gpio-controller@2 {
271 compatible = "snps,dw-apb-gpio-bank";
272 gpio-controller;
273 #gpio-cells = <2>;
274 gpio-generic,nr-gpio = <30>;
276 regoffset-dat = <0x5c>;
277 regoffset-set = <0x24>;
278 regoffset-dirout = <0x28>;
283 compatible = "snps,dw-apb-uart";
285 interrupt-parent = <&vic1>;
287 clock-frequency = <3686400>;
288 reg-shift = <2>;
289 reg-io-width = <4>;
293 compatible = "snps,dw-apb-uart";
295 interrupt-parent = <&vic1>;
297 clock-frequency = <3686400>;
298 reg-shift = <2>;
299 reg-io-width = <4>;
303 compatible = "snps,dw-apb-wdg";
305 interrupt-parent = <&vic0>;
307 bus-clock = <&pclk>, "bus";
311 compatible = "picochip,pc3x2-timer";
312 interrupt-parent = <&vic0>;
314 clock-freq = <200000000>;
319 compatible = "picochip,pc3x2-timer";
320 interrupt-parent = <&vic0>;
322 clock-freq = <200000000>;
328 rwid-axi {
329 #address-cells = <1>;
330 #size-cells = <1>;
331 compatible = "simple-bus";
335 compatible = "simple-bus";
336 #address-cells = <2>;
337 #size-cells = <1>;
345 compatible = "picochip,axi2pico-pc3x3";
347 interrupt-parent = <&vic0>;
352 compatible = "picochip,otp-pc3x3";