Lines Matching full:assigned
161 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
162 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
163 assigned-clock-rates = <24000000>;
173 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
174 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
175 assigned-clock-rates = <48000000>;
182 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
183 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
233 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
234 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
249 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
250 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
287 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
288 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
336 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
337 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
338 assigned-clock-rates = <48000000>;
348 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
349 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
350 assigned-clock-rates = <48000000>;
360 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
361 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
362 assigned-clock-rates = <48000000>;
372 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
373 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
374 assigned-clock-rates = <48000000>;