Lines Matching +full:non +full:- +full:armv7
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 #include <dt-bindings/reset/imx7-reset.h>
12 clock-frequency = <996000000>;
13 operating-points-v2 = <&cpu0_opp_table>;
14 #cooling-cells = <2>;
15 nvmem-cells = <&cpu_speed_grade>;
16 nvmem-cell-names = "speed_grade";
20 compatible = "arm,cortex-a7";
23 clock-frequency = <996000000>;
24 operating-points-v2 = <&cpu0_opp_table>;
25 cpu-idle-states = <&cpu_sleep_wait>;
30 compatible = "arm,armv7-timer";
31 interrupt-parent = <&intc>;
38 cpu0_opp_table: opp-table {
39 compatible = "operating-points-v2";
40 opp-shared;
42 opp-792000000 {
43 opp-hz = /bits/ 64 <792000000>;
44 opp-microvolt = <1000000>;
45 clock-latency-ns = <150000>;
46 opp-supported-hw = <0xf>, <0xf>;
49 opp-996000000 {
50 opp-hz = /bits/ 64 <996000000>;
51 opp-microvolt = <1100000>;
52 clock-latency-ns = <150000>;
53 opp-supported-hw = <0xc>, <0xf>;
56 opp-1200000000 {
57 opp-hz = /bits/ 64 <1200000000>;
58 opp-microvolt = <1225000>;
59 clock-latency-ns = <150000>;
60 opp-supported-hw = <0x8>, <0xf>;
65 compatible = "usb-nop-xceiv";
67 clock-names = "main_clk";
68 #phy-cells = <0>;
73 compatible = "arm,coresight-etm3x", "arm,primecell";
78 * without arm,primecell-periphid because amba bus try to
81 arm,primecell-periphid = <0xbb956>;
84 clock-names = "apb_pclk";
86 out-ports {
89 remote-endpoint = <&ca_funnel_in_port1>;
95 intc: interrupt-controller@31001000 {
96 compatible = "arm,cortex-a7-gic";
98 #interrupt-cells = <3>;
99 interrupt-controller;
100 interrupt-parent = <&intc>;
110 pcie_phy: pcie-phy@306d0000 {
111 compatible = "fsl,imx7d-pcie-phy";
119 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
125 phy-clkgate-delay-us = <400>;
130 #index-cells = <1>;
131 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
136 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
138 interrupt-names = "int0", "int1", "int2", "pps";
148 clock-names = "ipg", "ahb", "ptp",
150 fsl,num-tx-queues = <3>;
151 fsl,num-rx-queues = <3>;
156 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
159 reg-names = "dbi", "config";
160 #address-cells = <3>;
161 #size-cells = <2>;
163 bus-range = <0x00 0xff>;
165 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
166 num-lanes = <1>;
167 num-viewport = <4>;
169 interrupt-names = "msi";
170 #interrupt-cells = <1>;
171 interrupt-map-mask = <0 0 0 0x7>;
176 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
183 clock-names = "pcie", "pcie_bus", "pcie_phy";
184 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
186 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
189 fsl,max-link-speed = <2>;
190 power-domains = <&pgc_pcie_phy>;
194 reset-names = "pciephy", "apps", "turnoff";
195 fsl,imx7d-pcie-phy = <&pcie_phy>;
201 #address-cells = <1>;
202 #size-cells = <0>;
207 remote-endpoint = <&etm1_out_port>;