Lines Matching full:assigned
75 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
77 assigned-clock-parents = <&clks IMX7D_CKIL>;
78 assigned-clock-rates = <0>, <32768>;
91 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
93 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
94 assigned-clock-rates = <0>, <100000000>;
236 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
238 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
239 assigned-clock-rates = <0>, <24576000>;
269 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
270 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
277 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
278 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
286 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
335 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
336 assigned-clock-rates = <400000000>;