Lines Matching +full:clock +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a7";
57 clock-frequency = <1000000000>;
59 clock-names = "cpu";
60 #cooling-cells = <2>;
62 operating-points = <
78 compatible = "arm,cortex-a7";
80 clock-frequency = <1000000000>;
82 clock-names = "cpu";
83 #cooling-cells = <2>;
85 operating-points = <
100 fixed-rate-clocks {
101 #address-cells = <1>;
102 #size-cells = <0>;
104 xusbxti: clock@0 {
105 compatible = "fixed-clock";
107 clock-frequency = <0>;
108 #clock-cells = <0>;
109 clock-output-names = "xusbxti";
112 xxti: clock@1 {
113 compatible = "fixed-clock";
115 clock-frequency = <0>;
116 #clock-cells = <0>;
117 clock-output-names = "xxti";
120 xtcxo: clock@2 {
121 compatible = "fixed-clock";
123 clock-frequency = <0>;
124 #clock-cells = <0>;
125 clock-output-names = "xtcxo";
130 compatible = "arm,cortex-a7-pmu";
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
142 compatible = "mmio-sram";
144 #address-cells = <1>;
145 #size-cells = <1>;
148 smp-sysram@0 {
149 compatible = "samsung,exynos4210-sysram";
153 smp-sysram@3f000 {
154 compatible = "samsung,exynos4210-sysram-ns";
160 compatible = "samsung,exynos4210-chipid";
165 compatible = "samsung,exynos3-sysreg", "syscon";
169 pmu_system_controller: system-controller@10020000 {
170 compatible = "samsung,exynos3250-pmu", "syscon";
172 interrupt-controller;
173 #interrupt-cells = <3>;
174 interrupt-parent = <&gic>;
175 clock-names = "clkout8";
177 #clock-cells = <1>;
180 mipi_phy: video-phy {
181 compatible = "samsung,s5pv210-mipi-video-phy";
182 #phy-cells = <1>;
186 pd_cam: power-domain@10023c00 {
187 compatible = "samsung,exynos4210-pd";
189 #power-domain-cells = <0>;
193 pd_mfc: power-domain@10023c40 {
194 compatible = "samsung,exynos4210-pd";
196 #power-domain-cells = <0>;
200 pd_g3d: power-domain@10023c60 {
201 compatible = "samsung,exynos4210-pd";
203 #power-domain-cells = <0>;
207 pd_lcd0: power-domain@10023c80 {
208 compatible = "samsung,exynos4210-pd";
210 #power-domain-cells = <0>;
214 pd_isp: power-domain@10023ca0 {
215 compatible = "samsung,exynos4210-pd";
217 #power-domain-cells = <0>;
221 cmu: clock-controller@10030000 {
222 compatible = "samsung,exynos3250-cmu";
224 #clock-cells = <1>;
225 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
227 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
231 cmu_dmc: clock-controller@105c0000 {
232 compatible = "samsung,exynos3250-cmu-dmc";
234 #clock-cells = <1>;
238 compatible = "samsung,s3c6410-rtc";
242 interrupt-parent = <&pmu_system_controller>;
247 compatible = "samsung,exynos3250-tmu";
251 clock-names = "tmu_apbif";
252 #thermal-sensor-cells = <0>;
256 gic: interrupt-controller@10481000 {
257 compatible = "arm,cortex-a15-gic";
258 #interrupt-cells = <3>;
259 interrupt-controller;
269 compatible = "samsung,exynos4210-mct";
280 clock-names = "fin_pll", "mct";
284 compatible = "samsung,exynos3250-pinctrl";
288 wakeup-interrupt-controller {
289 compatible = "samsung,exynos4210-wakeup-eint";
295 compatible = "samsung,exynos3250-pinctrl";
301 compatible = "samsung,exynos3250-jpeg";
305 clock-names = "jpeg", "sclk";
306 power-domains = <&pd_cam>;
307 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
308 assigned-clock-rates = <0>, <150000000>;
309 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
315 compatible = "samsung,exynos-sysmmu";
319 clock-names = "sysmmu", "master";
321 power-domains = <&pd_cam>;
322 #iommu-cells = <0>;
326 compatible = "samsung,exynos3250-fimd";
328 interrupt-names = "fifo", "vsync", "lcd_sys";
333 clock-names = "sclk_fimd", "fimd";
334 power-domains = <&pd_lcd0>;
341 compatible = "samsung,exynos3250-mipi-dsi";
344 samsung,phy-type = <0>;
345 power-domains = <&pd_lcd0>;
347 phy-names = "dsim";
349 clock-names = "bus_clk", "pll_clk";
350 #address-cells = <1>;
351 #size-cells = <0>;
356 compatible = "samsung,exynos-sysmmu";
360 clock-names = "sysmmu", "master";
362 power-domains = <&pd_lcd0>;
363 #iommu-cells = <0>;
367 compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
371 clock-names = "otg";
373 phy-names = "usb2-phy";
378 compatible = "samsung,exynos5420-dw-mshc";
382 clock-names = "biu", "ciu";
383 fifo-depth = <0x80>;
384 #address-cells = <1>;
385 #size-cells = <0>;
390 compatible = "samsung,exynos5420-dw-mshc";
394 clock-names = "biu", "ciu";
395 fifo-depth = <0x80>;
396 #address-cells = <1>;
397 #size-cells = <0>;
402 compatible = "samsung,exynos5250-dw-mshc";
406 clock-names = "biu", "ciu";
407 fifo-depth = <0x80>;
408 #address-cells = <1>;
409 #size-cells = <0>;
413 exynos_usbphy: exynos-usbphy@125b0000 {
414 compatible = "samsung,exynos3250-usb2-phy";
416 samsung,pmureg-phandle = <&pmu_system_controller>;
418 clock-names = "phy", "ref";
419 #phy-cells = <1>;
424 compatible = "simple-bus";
425 #address-cells = <1>;
426 #size-cells = <1>;
434 clock-names = "apb_pclk";
435 #dma-cells = <1>;
436 #dma-channels = <8>;
437 #dma-requests = <32>;
445 clock-names = "apb_pclk";
446 #dma-cells = <1>;
447 #dma-channels = <8>;
448 #dma-requests = <32>;
453 compatible = "samsung,exynos3250-adc";
456 clock-names = "adc", "sclk";
458 #io-channel-cells = <1>;
459 io-channel-ranges;
460 samsung,syscon-phandle = <&pmu_system_controller>;
465 compatible = "samsung,exynos4210-mali", "arm,mali-400";
478 interrupt-names = "gp",
491 clock-names = "bus", "core";
492 power-domains = <&pd_g3d>;
494 /* TODO: operating points for DVFS, assigned clock as 134 MHz */
498 compatible = "samsung,mfc-v7";
501 clock-names = "mfc", "sclk_mfc";
503 power-domains = <&pd_mfc>;
508 compatible = "samsung,exynos-sysmmu";
512 clock-names = "sysmmu", "master";
514 power-domains = <&pd_mfc>;
515 #iommu-cells = <0>;
519 compatible = "samsung,exynos4210-uart";
523 clock-names = "uart", "clk_uart_baud0";
524 pinctrl-names = "default";
525 pinctrl-0 = <&uart0_data &uart0_fctl>;
530 compatible = "samsung,exynos4210-uart";
534 clock-names = "uart", "clk_uart_baud0";
535 pinctrl-names = "default";
536 pinctrl-0 = <&uart1_data>;
541 compatible = "samsung,exynos4210-uart";
545 clock-names = "uart", "clk_uart_baud0";
546 pinctrl-names = "default";
547 pinctrl-0 = <&uart2_data>;
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "samsung,s3c2440-i2c";
558 clock-names = "i2c";
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c0_bus>;
565 #address-cells = <1>;
566 #size-cells = <0>;
567 compatible = "samsung,s3c2440-i2c";
571 clock-names = "i2c";
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c1_bus>;
578 #address-cells = <1>;
579 #size-cells = <0>;
580 compatible = "samsung,s3c2440-i2c";
584 clock-names = "i2c";
585 pinctrl-names = "default";
586 pinctrl-0 = <&i2c2_bus>;
591 #address-cells = <1>;
592 #size-cells = <0>;
593 compatible = "samsung,s3c2440-i2c";
597 clock-names = "i2c";
598 pinctrl-names = "default";
599 pinctrl-0 = <&i2c3_bus>;
604 #address-cells = <1>;
605 #size-cells = <0>;
606 compatible = "samsung,s3c2440-i2c";
610 clock-names = "i2c";
611 pinctrl-names = "default";
612 pinctrl-0 = <&i2c4_bus>;
617 #address-cells = <1>;
618 #size-cells = <0>;
619 compatible = "samsung,s3c2440-i2c";
623 clock-names = "i2c";
624 pinctrl-names = "default";
625 pinctrl-0 = <&i2c5_bus>;
630 #address-cells = <1>;
631 #size-cells = <0>;
632 compatible = "samsung,s3c2440-i2c";
636 clock-names = "i2c";
637 pinctrl-names = "default";
638 pinctrl-0 = <&i2c6_bus>;
643 #address-cells = <1>;
644 #size-cells = <0>;
645 compatible = "samsung,s3c2440-i2c";
649 clock-names = "i2c";
650 pinctrl-names = "default";
651 pinctrl-0 = <&i2c7_bus>;
656 compatible = "samsung,exynos4210-spi";
660 dma-names = "tx", "rx";
661 #address-cells = <1>;
662 #size-cells = <0>;
664 clock-names = "spi", "spi_busclk0";
665 samsung,spi-src-clk = <0>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&spi0_bus>;
672 compatible = "samsung,exynos4210-spi";
676 dma-names = "tx", "rx";
677 #address-cells = <1>;
678 #size-cells = <0>;
680 clock-names = "spi", "spi_busclk0";
681 samsung,spi-src-clk = <0>;
682 pinctrl-names = "default";
683 pinctrl-0 = <&spi1_bus>;
688 compatible = "samsung,s3c6410-i2s";
692 clock-names = "iis", "i2s_opclk0";
694 dma-names = "tx", "rx";
695 pinctrl-0 = <&i2s2_bus>;
696 pinctrl-names = "default";
701 compatible = "samsung,exynos4210-pwm";
708 #pwm-cells = <3>;
713 compatible = "samsung,exynos-ppmu";
719 compatible = "samsung,exynos-ppmu";
725 compatible = "samsung,exynos-ppmu";
731 compatible = "samsung,exynos-ppmu";
734 clock-names = "ppmu";
739 compatible = "samsung,exynos-ppmu";
742 clock-names = "ppmu";
747 compatible = "samsung,exynos-ppmu";
750 clock-names = "ppmu";
755 compatible = "samsung,exynos-ppmu";
758 clock-names = "ppmu";
763 compatible = "samsung,exynos-ppmu";
766 clock-names = "ppmu";
771 compatible = "samsung,exynos-ppmu";
774 clock-names = "ppmu";
779 compatible = "samsung,exynos-ppmu";
782 clock-names = "ppmu";
787 compatible = "samsung,exynos-bus";
789 clock-names = "bus";
790 operating-points-v2 = <&bus_dmc_opp_table>;
795 compatible = "operating-points-v2";
796 opp-shared;
798 opp-50000000 {
799 opp-hz = /bits/ 64 <50000000>;
800 opp-microvolt = <800000>;
802 opp-100000000 {
803 opp-hz = /bits/ 64 <100000000>;
804 opp-microvolt = <800000>;
806 opp-134000000 {
807 opp-hz = /bits/ 64 <134000000>;
808 opp-microvolt = <800000>;
810 opp-200000000 {
811 opp-hz = /bits/ 64 <200000000>;
812 opp-microvolt = <825000>;
814 opp-400000000 {
815 opp-hz = /bits/ 64 <400000000>;
816 opp-microvolt = <875000>;
821 compatible = "samsung,exynos-bus";
823 clock-names = "bus";
824 operating-points-v2 = <&bus_leftbus_opp_table>;
829 compatible = "samsung,exynos-bus";
831 clock-names = "bus";
832 operating-points-v2 = <&bus_leftbus_opp_table>;
837 compatible = "samsung,exynos-bus";
839 clock-names = "bus";
840 operating-points-v2 = <&bus_leftbus_opp_table>;
845 compatible = "samsung,exynos-bus";
847 clock-names = "bus";
848 operating-points-v2 = <&bus_leftbus_opp_table>;
853 compatible = "samsung,exynos-bus";
855 clock-names = "bus";
856 operating-points-v2 = <&bus_mcuisp_opp_table>;
861 compatible = "samsung,exynos-bus";
863 clock-names = "bus";
864 operating-points-v2 = <&bus_isp_opp_table>;
869 compatible = "samsung,exynos-bus";
871 clock-names = "bus";
872 operating-points-v2 = <&bus_peril_opp_table>;
877 compatible = "samsung,exynos-bus";
879 clock-names = "bus";
880 operating-points-v2 = <&bus_leftbus_opp_table>;
885 compatible = "operating-points-v2";
886 opp-shared;
888 opp-50000000 {
889 opp-hz = /bits/ 64 <50000000>;
890 opp-microvolt = <900000>;
892 opp-80000000 {
893 opp-hz = /bits/ 64 <80000000>;
894 opp-microvolt = <900000>;
896 opp-100000000 {
897 opp-hz = /bits/ 64 <100000000>;
898 opp-microvolt = <1000000>;
900 opp-134000000 {
901 opp-hz = /bits/ 64 <134000000>;
902 opp-microvolt = <1000000>;
904 opp-200000000 {
905 opp-hz = /bits/ 64 <200000000>;
906 opp-microvolt = <1000000>;
911 compatible = "operating-points-v2";
912 opp-shared;
914 opp-50000000 {
915 opp-hz = /bits/ 64 <50000000>;
917 opp-80000000 {
918 opp-hz = /bits/ 64 <80000000>;
920 opp-100000000 {
921 opp-hz = /bits/ 64 <100000000>;
923 opp-200000000 {
924 opp-hz = /bits/ 64 <200000000>;
926 opp-400000000 {
927 opp-hz = /bits/ 64 <400000000>;
932 compatible = "operating-points-v2";
933 opp-shared;
935 opp-50000000 {
936 opp-hz = /bits/ 64 <50000000>;
938 opp-80000000 {
939 opp-hz = /bits/ 64 <80000000>;
941 opp-100000000 {
942 opp-hz = /bits/ 64 <100000000>;
944 opp-200000000 {
945 opp-hz = /bits/ 64 <200000000>;
947 opp-300000000 {
948 opp-hz = /bits/ 64 <300000000>;
953 compatible = "operating-points-v2";
954 opp-shared;
956 opp-50000000 {
957 opp-hz = /bits/ 64 <50000000>;
959 opp-80000000 {
960 opp-hz = /bits/ 64 <80000000>;
962 opp-100000000 {
963 opp-hz = /bits/ 64 <100000000>;
969 #include "exynos3250-pinctrl.dtsi"
970 #include "exynos-syscon-restart.dtsi"