Lines Matching full:r0
74 mov r0, \val
79 mov r0, \val
92 mrc p15, 0, r0, c1, c0
93 kphex r0, 8 /* control reg */
109 mov r0, r4
206 mov r0, #0x17 @ angel_SWIreason_EnterSVC
210 safe_svcmode_maskall r0
258 mov r0, pc
259 cmp r0, r4
260 ldrcc r0, LC0+32
261 addcc r0, r0, pc
262 cmpcc r4, r0
266 restart: adr r0, LC0
267 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
268 ldr sp, [r0, #28]
274 sub r0, r0, r1 @ calculate the delta offset
275 add r6, r6, r0 @ _edata
276 add r10, r10, r0 @ inflated kernel size location
293 add sp, sp, r0
307 * r0 = delta
366 stmfd sp!, {r0-r3, ip, lr}
367 mov r0, r8
377 cmp r0, #1
378 sub r0, r4, #TEXT_OFFSET
379 bic r0, r0, #1
380 add r0, r0, #0x100
385 ldmfd sp!, {r0-r3, ip, lr}
463 mrs r0, spsr
464 and r0, r0, #MODE_MASK
465 cmp r0, #HYP_MODE
475 0: adr r0, 0b
478 add r0, r0, r1
479 sub r0, r0, r5
480 add r0, r0, r10
505 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
507 stmdb r9!, {r0 - r3, r10 - r12, lr}
520 badr r0, restart
521 add r0, r0, r6
522 mov pc, r0
527 * r0 = delta
538 orrs r1, r0, r5
541 add r11, r11, r0
542 add r12, r12, r0
550 add r2, r2, r0
551 add r3, r3, r0
558 add r1, r1, r0 @ This fixes up C references
579 addlo r1, r1, r0 @ table. This fixes up the
585 not_relocated: mov r0, #0
586 1: str r0, [r2], #4 @ clear bss
587 str r0, [r2], #4
588 str r0, [r2], #4
589 str r0, [r2], #4
609 mov r0, r4
618 mrs r0, spsr @ Get saved CPU boot mode
619 and r0, r0, #MODE_MASK
620 cmp r0, #HYP_MODE @ if not booted in HYP mode...
624 ldr r0, [r12]
625 add r0, r0, r12
653 params: ldr r0, =0x10000100 @ params_phys for RPC
672 * r0, r1, r2, r3, r9, r10, r12 corrupted
685 mov r0, #0x3f @ 4G, the whole
686 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
687 mcr p15, 0, r0, c6, c7, 1
689 mov r0, #0x80 @ PR7
690 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
691 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
692 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
694 mov r0, #0xc000
695 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
696 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
698 mov r0, #0
699 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
700 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
701 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
702 mrc p15, 0, r0, c1, c0, 0 @ read control reg
704 orr r0, r0, #0x002d @ .... .... ..1. 11.1
705 orr r0, r0, #0x1000 @ ...1 .... .... ....
707 mcr p15, 0, r0, c1, c0, 0 @ write control reg
709 mov r0, #0
710 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
711 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
715 mov r0, #0x3f @ 4G, the whole
716 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
718 mov r0, #0x80 @ PR7
719 mcr p15, 0, r0, c2, c0, 0 @ cache on
720 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
722 mov r0, #0xc000
723 mcr p15, 0, r0, c5, c0, 0 @ access permission
725 mov r0, #0
726 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
731 mrc p15, 0, r0, c1, c0, 0 @ read control reg
733 orr r0, r0, #0x000d @ .... .... .... 11.1
735 mov r0, #0
736 mcr p15, 0, r0, c1, c0, 0 @ write control reg
739 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
755 mov r0, r3
756 mov r9, r0, lsr #18
767 str r1, [r0], #4 @ 1:1 mapping
769 teq r0, r2
782 add r0, r3, r2, lsl #2
783 str r1, [r0], #4
785 str r1, [r0]
792 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
793 bic r0, r0, #2 @ A (no unaligned access fault)
794 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
795 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
800 mov r0, #4 @ put dcache in WT mode
801 mcr p15, 7, r0, c15, c0, 0
809 mov r0, #0
810 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
811 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
812 mrc p15, 0, r0, c1, c0, 0 @ read control reg
813 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
814 orr r0, r0, #0x0030
815 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
817 mov r0, #0
818 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
829 mov r0, #0
830 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
832 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
834 mrc p15, 0, r0, c1, c0, 0 @ read control reg
835 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
836 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
837 orr r0, r0, #0x003c @ write buffer
838 bic r0, r0, #2 @ A (no unaligned access fault)
839 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
842 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
844 orrne r0, r0, #1 @ MMU enabled
852 mcr p15, 0, r0, c7, c5, 4 @ ISB
853 mcr p15, 0, r0, c1, c0, 0 @ load control register
854 mrc p15, 0, r0, c1, c0, 0 @ and read it back
855 mov r0, #0
856 mcr p15, 0, r0, c7, c5, 4 @ ISB
863 mov r0, #0
864 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
865 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
866 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
867 mrc p15, 0, r0, c1, c0, 0 @ read control reg
868 orr r0, r0, #0x1000 @ I-cache enable
870 mov r0, #0
871 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
877 orr r0, r0, #0x000d @ Write buffer, mmu
884 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
885 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
886 sub pc, lr, r0, lsr #32 @ properly flush pipeline
1105 * r0, r1, r2, r3, r9, r12 corrupted
1114 mrc p15, 0, r0, c1, c0
1115 bic r0, r0, #0x000d
1116 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1117 mov r0, #0
1118 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1119 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1120 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1124 mrc p15, 0, r0, c1, c0
1125 bic r0, r0, #0x000d
1126 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1127 mov r0, #0
1128 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1133 mrc p15, 0, r0, c1, c0
1134 bic r0, r0, #0x000d
1135 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1136 mov r0, #0
1137 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1138 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1143 mrc p15, 0, r0, c1, c0
1145 bic r0, r0, #0x000d
1147 bic r0, r0, #0x000c
1149 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1152 mov r0, #0
1154 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1156 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1157 mcr p15, 0, r0, c7, c10, 4 @ DSB
1158 mcr p15, 0, r0, c7, c5, 4 @ ISB
1222 stmfd sp!, {r0-r7, r9-r11}
1223 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1224 ands r3, r0, #0x7000000 @ extract loc from clidr
1230 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1263 ldmfd sp!, {r0-r7, r9-r11}
1278 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1279 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1334 @ phex corrupts {r0, r1, r2, r3}
1339 movmi r0, r3
1341 and r2, r0, #15
1342 mov r0, r0, lsr #4
1349 @ puts corrupts {r0, r1, r2, r3}
1351 1: ldrb r2, [r0], #1
1361 teq r0, #0
1364 @ putc corrupts {r0, r1, r2, r3}
1366 mov r2, r0
1367 loadsp r3, r1, r0
1368 mov r0, #0
1371 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1372 memdump: mov r12, r0
1375 2: mov r0, r11, lsl #2
1376 add r0, r0, r12
1379 mov r0, #':'
1381 1: mov r0, #' '
1383 ldr r0, [r12, r11, lsl #2]
1386 and r0, r11, #7
1387 teq r0, #3
1388 moveq r0, #' '
1390 and r0, r11, #7
1392 teq r0, #7
1394 mov r0, #'\n'
1417 mov r0, #0 @ must be 0
1434 @ is passed in r2. r0 and r1 are passed through from the
1443 @ Check for error return from EFI stub. r0 has FDT address
1445 cmn r0, #1
1449 mov r4, r0
1469 @ r1 is the machine type, and r0 needs to be 0
1470 mov r0, #0
1482 ldr r0, =0x80000001