Lines Matching +full:no +full:- +full:pc +full:- +full:write
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
14 AR_CLASS( .arch armv7-a )
15 M_CLASS( .arch armv7-m )
97 kputc #'-'
125 kputc #'-'
129 kputc #'-'
134 kputc #'-'
174 AR_CLASS( sub pc, pc, #3 ) @ A/R: switch to Thumb2 mode
199 * Booting from Angel - need to enter SVC mode and disable
216 * be needed here - is there an Angel SWI call for this?
234 * different platforms - we have chosen 128MB to allow
244 mov r4, pc
254 * That means r4 < pc || r4 - 16k page directory > &_end.
258 mov r0, pc
261 addcc r0, r0, pc
281 * in little-endian form.
339 * and folded into the former here. No GOT fixup has occurred
355 /* preserve 64-bit alignment */
366 stmfd sp!, {r0-r3, ip, lr}
373 * If returned value is 1, there is no ATAG at the location
385 ldmfd sp!, {r0-r3, ip, lr}
413 /* preserve 64-bit alignment */
430 * r4 - 16k page directory >= r10 -> OK
431 * r4 + image length <= address of wont_overwrite -> OK
450 * Bump to the next 256-byte boundary with the size of
454 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
471 * reference __hyp_stub_vectors in a PC-relative way.
476 movw r1, #:lower16:__hyp_stub_vectors - 0b
477 movt r1, #:upper16:__hyp_stub_vectors - 0b
505 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
507 stmdb r9!, {r0 - r3, r10 - r12, lr}
522 mov pc, r0
633 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
644 .word input_data_end - 4 @ r10 (inflated size location)
648 .word _end - restart + 16384 + 1024*1024
649 .size LC0, . - LC0
654 mov pc, lr
690 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
691 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
692 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
695 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
696 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
699 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
700 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
701 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
707 mcr p15, 0, r0, c1, c0, 0 @ write control reg
710 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
711 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
712 mov pc, lr
720 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
736 mcr p15, 0, r0, c1, c0, 0 @ write control reg
740 mov pc, lr
765 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
774 * so there is no map overlap problem for up to 1 MB compressed kernel.
779 mov r2, pc
786 mov pc, lr
793 bic r0, r0, #2 @ A (no unaligned access fault)
795 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
810 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
813 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
815 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
820 mov pc, r12
830 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
836 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
837 orr r0, r0, #0x003c @ write buffer
838 bic r0, r0, #2 @ A (no unaligned access fault)
842 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
846 bic r6, r6, #1 << 31 @ 32-bit translation system
857 mov pc, r12
865 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
868 orr r0, r0, #0x1000 @ I-cache enable
872 mov pc, r12
877 orr r0, r0, #0x000d @ Write buffer, mmu
879 mov r1, #-1
886 sub pc, lr, r0, lsr #32 @ properly flush pipeline
910 * On v7-M the processor id is located in the V7M_SCB_CPUID
912 * v7-M (if existant at all) we just return early here.
915 * use cp15 registers that are not implemented on v7-M.
925 ARM( addeq pc, r12, r3 ) @ call cache function
927 THUMB( moveq pc, r12 ) @ call cache function
933 * - CPU ID match
934 * - CPU ID mask
935 * - 'cache on' method instruction
936 * - 'cache off' method instruction
937 * - 'cache flush' method instruction
950 mov pc, lr
952 mov pc, lr
954 mov pc, lr
959 mov pc, lr
961 mov pc, lr
963 mov pc, lr
970 mov pc, lr
985 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
993 mov pc, lr
995 mov pc, lr
997 mov pc, lr
1081 mov pc, lr
1083 mov pc, lr
1085 mov pc, lr
1088 .size proc_types, . - proc_types
1091 * If you get a "non-constant expression in ".if" statement"
1096 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1118 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1119 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1120 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1121 mov pc, lr
1129 mov pc, lr
1140 mov pc, lr
1159 mov pc, r12
1176 movne pc, lr
1191 mov pc, lr
1195 movne pc, lr
1200 mov pc, lr
1209 mov pc, lr
1222 stmfd sp!, {r0-r7, r9-r11}
1226 beq finished @ if loc is 0, then no need to clean
1233 blt skip @ skip if no cache, or just i-cache
1263 ldmfd sp!, {r0-r7, r9-r11}
1271 mov pc, lr
1275 movne pc, lr
1280 mov pc, lr
1284 movne pc, lr
1301 mov r1, pc
1314 mov pc, lr
1319 movne pc, lr
1322 mov pc, lr
1332 .size phexbuf, . - phexbuf
1353 moveq pc, lr
1363 mov pc, lr
1398 mov pc, r10
1420 ARM( mov pc, r4 ) @ call kernel
1428 _start: .long start - .
1460 mcr p15, 0, r1, c1, c0, 0 @ write SCTLR
1478 mov pc, lr @ no mode switch
1483 ldmfd sp!, {ip, pc}