Lines Matching refs:erratum

847 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
856 	  r1p* erratum. If a code sequence containing an ARM/Thumb
873 	  erratum. For very specific sequences of memory operations, it is
887 	  erratum. Any asynchronous access to the L2 cache may encounter a
900 	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
913 	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
928 	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
938 	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
940 	  As a consequence of this erratum, some TLB entries which should be
951 	  (r2p*) erratum. Under very rare conditions, a faulty
965 	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
975 	  r3p*) erratum. A speculative memory access may cause a page table walk
986 	  r2p0) erratum. The Store Buffer does not have any automatic draining
997 	  r0p2 erratum (possible cache data corruption with
1008 	  This option enables the workaround for erratum 764369
1023 	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1034 	  option enables the Linux kernel workaround for this erratum
1043 	  (up to r0p4) erratum. In certain rare sequences of code, the
1045 	  workaround disables the loop buffer to avoid the erratum.
1066 	  (all revs) erratum. In very rare timing conditions, a sequence
1076 	  (all revs) erratum. Within rare timing constraints, executing a
1085 	  (all revs) erratum. Under very rare timing conditions, the CPU might
1093 	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1105 	  This is identical to Cortex-A12 erratum 852422.  It is a separate
1106 	  config option from the A12 erratum due to the way errata are checked
1113 	  This option enables the workaround for the 857272 Cortex-A17 erratum.
1114 	  This erratum is not known to be fixed in any A17 revision.
1115 	  This is identical to Cortex-A12 erratum 857271.  It is a separate
1116 	  config option from the A12 erratum due to the way errata are checked
1162 	  However, because of this erratum, an L2 set/way cache maintenance