Lines Matching refs:errata

834 	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
843 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
852 	bool "ARM errata: Stale prediction on replaced interworking branch"
868 	bool "ARM errata: Processor deadlock when a false hazard is created"
882 	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
895 	bool "ARM errata: DMB operation may be faulty"
908 	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
923 	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
934 	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
946 	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
960 	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
971 	bool "ARM errata: possible faulty MMU translations following an ASID switch"
982 	bool "ARM errata: no automatic Store Buffer drain"
993 	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1005 	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1019        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1029 	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1039 	bool "ARM errata: incorrect instructions may be executed from loop buffer"
1048 	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1057 	  This workaround for all both errata involves setting bit[12] of the
1062 	bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1072 	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1081 	bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1089 	bool "ARM errata: A17: DMB ST might fail to create order between stores"
1098 	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1106 	  config option from the A12 erratum due to the way errata are checked
1110 	bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1116 	  config option from the A12 erratum due to the way errata are checked
1156 	bool "ARM errata: Cache maintenance by set/way operations can execute out of order"