Lines Matching refs:deadlock
868 bool "ARM errata: Processor deadlock when a false hazard is created"
876 hazard might then cause a processor deadlock. The workaround enables
1019 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1025 to deadlock. This workaround puts DSB before executing ISB if
1048 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1053 instruction might deadlock. Fixed in r0p1.
1055 lead to either a data corruption or a CPU deadlock. Not fixed in
1069 deadlock when the VMOV instructions are issued out-of-order.
1072 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1078 and Device/Strongly-Ordered loads and stores might cause deadlock
1081 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1098 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1103 lead to either a data corruption or a CPU deadlock. Not fixed in
1110 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"