Lines Matching +full:non +full:- +full:armv7
1 # SPDX-License-Identifier: GPL-2.0
126 The ARM series is a line of low-power-consumption RISC chip designs
128 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
129 manufactured, but legacy ARM-based PC hardware remains popular in
239 Patch phys-to-virt and virt-to-phys translation functions at
243 This can only be used with non-XIP MMU kernels where the base
291 bool "MMU-based Paged Memory Management Support"
294 Select if you want MMU-based virtualised addressing space
330 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
343 bool "EBSA-110"
352 from Digital. It has limited hardware on-board, including an
357 bool "EP93xx-based"
384 bool "IOP32x-based"
397 bool "IXP4xx-based"
433 bool "PXA2xx/PXA3xx-based"
471 On the Acorn Risc-PC, Linux can support the internal IDE disk and
472 CD-ROM interface, serial and parallel port, and the floppy drive.
475 bool "SA1100-based"
574 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
603 # This is sorted alphabetically by mach-* pathname. However, plat-*
605 # plat- suffix) or along side the corresponding mach-* source.
607 source "arch/arm/mach-actions/Kconfig"
609 source "arch/arm/mach-alpine/Kconfig"
611 source "arch/arm/mach-artpec/Kconfig"
613 source "arch/arm/mach-asm9260/Kconfig"
615 source "arch/arm/mach-aspeed/Kconfig"
617 source "arch/arm/mach-at91/Kconfig"
619 source "arch/arm/mach-axxia/Kconfig"
621 source "arch/arm/mach-bcm/Kconfig"
623 source "arch/arm/mach-berlin/Kconfig"
625 source "arch/arm/mach-clps711x/Kconfig"
627 source "arch/arm/mach-cns3xxx/Kconfig"
629 source "arch/arm/mach-davinci/Kconfig"
631 source "arch/arm/mach-digicolor/Kconfig"
633 source "arch/arm/mach-dove/Kconfig"
635 source "arch/arm/mach-ep93xx/Kconfig"
637 source "arch/arm/mach-exynos/Kconfig"
638 source "arch/arm/plat-samsung/Kconfig"
640 source "arch/arm/mach-footbridge/Kconfig"
642 source "arch/arm/mach-gemini/Kconfig"
644 source "arch/arm/mach-highbank/Kconfig"
646 source "arch/arm/mach-hisi/Kconfig"
648 source "arch/arm/mach-imx/Kconfig"
650 source "arch/arm/mach-integrator/Kconfig"
652 source "arch/arm/mach-iop32x/Kconfig"
654 source "arch/arm/mach-ixp4xx/Kconfig"
656 source "arch/arm/mach-keystone/Kconfig"
658 source "arch/arm/mach-lpc32xx/Kconfig"
660 source "arch/arm/mach-mediatek/Kconfig"
662 source "arch/arm/mach-meson/Kconfig"
664 source "arch/arm/mach-milbeaut/Kconfig"
666 source "arch/arm/mach-mmp/Kconfig"
668 source "arch/arm/mach-moxart/Kconfig"
670 source "arch/arm/mach-mv78xx0/Kconfig"
672 source "arch/arm/mach-mvebu/Kconfig"
674 source "arch/arm/mach-mxs/Kconfig"
676 source "arch/arm/mach-nomadik/Kconfig"
678 source "arch/arm/mach-npcm/Kconfig"
680 source "arch/arm/mach-nspire/Kconfig"
682 source "arch/arm/plat-omap/Kconfig"
684 source "arch/arm/mach-omap1/Kconfig"
686 source "arch/arm/mach-omap2/Kconfig"
688 source "arch/arm/mach-orion5x/Kconfig"
690 source "arch/arm/mach-oxnas/Kconfig"
692 source "arch/arm/mach-picoxcell/Kconfig"
694 source "arch/arm/mach-prima2/Kconfig"
696 source "arch/arm/mach-pxa/Kconfig"
697 source "arch/arm/plat-pxa/Kconfig"
699 source "arch/arm/mach-qcom/Kconfig"
701 source "arch/arm/mach-rda/Kconfig"
703 source "arch/arm/mach-realview/Kconfig"
705 source "arch/arm/mach-rockchip/Kconfig"
707 source "arch/arm/mach-s3c24xx/Kconfig"
709 source "arch/arm/mach-s3c64xx/Kconfig"
711 source "arch/arm/mach-s5pv210/Kconfig"
713 source "arch/arm/mach-sa1100/Kconfig"
715 source "arch/arm/mach-shmobile/Kconfig"
717 source "arch/arm/mach-socfpga/Kconfig"
719 source "arch/arm/mach-spear/Kconfig"
721 source "arch/arm/mach-sti/Kconfig"
723 source "arch/arm/mach-stm32/Kconfig"
725 source "arch/arm/mach-sunxi/Kconfig"
727 source "arch/arm/mach-tango/Kconfig"
729 source "arch/arm/mach-tegra/Kconfig"
731 source "arch/arm/mach-u300/Kconfig"
733 source "arch/arm/mach-uniphier/Kconfig"
735 source "arch/arm/mach-ux500/Kconfig"
737 source "arch/arm/mach-versatile/Kconfig"
739 source "arch/arm/mach-vexpress/Kconfig"
740 source "arch/arm/plat-versatile/Kconfig"
742 source "arch/arm/mach-vt8500/Kconfig"
744 source "arch/arm/mach-zx/Kconfig"
746 source "arch/arm/mach-zynq/Kconfig"
748 # ARMv7-M architecture
765 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
774 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
775 with a range of available cores like Cortex-M3/M4/M7.
816 source "arch/arm/Kconfig-nommu"
834 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
837 Executing a SWP instruction to read-only memory does not set bit 11
855 This option enables the workaround for the 430973 Cortex-A8
858 same virtual address, whether due to self-modifying code or virtual
859 to physical address re-mapping, Cortex-A8 does not recover from the
860 stale interworking branch prediction. This results in Cortex-A8
865 available in non-secure mode.
872 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
879 register may not be available in non-secure mode.
886 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
890 workaround disables the write-allocate mode for the L2 cache via the
892 may not be available in non-secure mode.
899 This option enables the workaround for the 742230 Cortex-A9
903 the diagnostic register of the Cortex-A9 which causes the DMB
912 This option enables the workaround for the 742231 Cortex-A9
914 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
919 register of the Cortex-A9 which reduces the linefill issuing
927 This option enables the workaround for the 643719 Cortex-A9 (prior to
937 This option enables the workaround for the 720789 Cortex-A9 (prior to
950 This option enables the workaround for the 743622 Cortex-A9
952 optimisation in the Cortex-A9 Store Buffer may lead to data
954 register of the Cortex-A9 which disables the Store Buffer
964 This option enables the workaround for the 751472 Cortex-A9 (prior
974 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
977 can populate the micro-TLB with a stale entry which may be hit with
985 This option enables the workaround for the 754327 Cortex-A9 (prior to
993 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
998 hit-under-miss enabled). It sets the undocumented bit 31 in
1000 register, thus disabling hit-under-miss without putting the
1009 affecting Cortex-A9 MPCore with two or more processors (all
1022 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1029 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1032 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1042 This option enables the workaround for the 773022 Cortex-A15
1052 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1054 - Cortex-A12 852422: Execution of a sequence of instructions might
1056 any Cortex-A12 cores yet.
1065 This option enables the workaround for the 821420 Cortex-A12
1069 deadlock when the VMOV instructions are issued out-of-order.
1075 This option enables the workaround for the 825619 Cortex-A12
1078 and Device/Strongly-Ordered loads and stores might cause deadlock
1084 This option enables the workaround for the 857271 Cortex-A12
1092 This option enables the workaround for the 852421 Cortex-A17
1102 - Cortex-A17 852423: Execution of a sequence of instructions might
1104 any Cortex-A17 cores yet.
1105 This is identical to Cortex-A12 erratum 852422. It is a separate
1113 This option enables the workaround for the 857272 Cortex-A17 erratum.
1115 This is identical to Cortex-A12 erratum 857271. It is a separate
1164 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1174 This option should be selected by machines which have an SMP-
1177 The only effect of this option is to make the SMP-related
1181 bool "Symmetric Multi-Processing"
1192 If you say N here, the kernel will run on uni- and multiprocessor
1198 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1199 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1200 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1209 SMP kernels contain instructions which fail on non-SMP processors.
1226 bool "Multi-core scheduler support"
1229 Multi-core scheduler support improves the CPU scheduler's decision
1230 making when dealing with multi-core CPU chips at a cost of slightly
1260 bool "Multi-Cluster Power Management"
1264 for (multi-)cluster based systems, such as big.LITTLE based
1331 int "Maximum number of CPUs (2-32)"
1337 bool "Support for hot-pluggable CPUs"
1350 implementing the PSCI specification for CPU-centric power
1420 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1426 Thumb-2 mode.
1431 bool "Work around buggy Thumb-2 short branch relocations in gas"
1435 Various binutils versions can resolve Thumb-2 branches to
1436 locally-defined, preemptible global symbols as short-range "b.n"
1450 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1455 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1457 Only Thumb-2 kernels are affected.
1504 (only for non "thumb" binaries). This option adds a tiny
1547 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1555 user-space 2nd level page tables to reside in high memory.
1558 bool "Enable use of CPU domains to implement privileged no-access"
1564 use-after-free bugs becoming an exploitable privilege escalation
1568 CPUs with low-vector mappings use a best-efforts implementation.
1601 Disabling this is usually safe for small single-platform
1628 address divisible by 4. On 32-bit ARM processors, these non-aligned
1631 correct operation of some network protocols. With an IP-only
1640 cores where a 8-word STM instruction give significantly higher
1647 However, if the CPU data cache is using a write-allocate mode,
1653 ---help---
1749 The physical address at which the ROM-able zImage is to be
1751 ROM-able zImage formats normally set this to a suitable
1761 for the ROM-able zImage which must be available while the
1764 Platforms which normally make use of ROM-able zImage formats
1816 Uses the command-line options passed by the boot loader instead of
1823 The command-line arguments provided by the boot loader will be
1834 architectures, you should supply some command-line options at build
1846 Uses the command-line options passed by the boot loader. If
1853 The command-line arguments provided by the boot loader will be
1862 command-line options your boot loader passes to the kernel.
1866 bool "Kernel Execute-In-Place from ROM"
1869 Execute-In-Place allows the kernel to run from non-volatile storage
1872 to RAM. Read-write sections, such as the data section and stack,
1934 loaded in the main kernel with kexec-tools into a specially
1939 For more details see Documentation/admin-guide/kdump/kdump.rst
1946 will be determined at run-time by masking the current IP with
1961 ---help---
1963 by UEFI firmware (such as non-volatile variables, realtime
1978 continue to boot on existing non-UEFI platforms.
1984 to be enabled much earlier than we do on ARM, which is non-trivial.
2003 ---help---
2007 your machine has an FPA or floating point co-processor podule.
2016 Say Y to include 80-bit support in the kernel floating-point
2017 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2018 Note that gcc does not generate 80-bit operations by default,
2027 ---help---
2031 It is very simple, and approximately 3-6 times faster than NWFPE.
2039 bool "VFP-format floating point maths"
2045 Please see <file:Documentation/arm/vfp/release-notes.rst> for
2059 Say Y to include support code for NEON, the ARMv7 Advanced SIMD