68 	iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);  in axs10x_enable_gpio_intc_wire()
69 	iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);  in axs10x_enable_gpio_intc_wire()
70 	iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);  in axs10x_enable_gpio_intc_wire()
71 	iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);  in axs10x_enable_gpio_intc_wire()
240 	iowrite32(slave_select, base + 0x0);	/* SLV0 */  in axs101_set_memmap()
241 	iowrite32(slave_offset, base + 0x8);	/* OFFSET0 */  in axs101_set_memmap()
249 	iowrite32(slave_select, base + 0x4);	/* SLV1 */  in axs101_set_memmap()
250 	iowrite32(slave_offset, base + 0xC);	/* OFFSET1 */  in axs101_set_memmap()
259 	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);  in axs101_early_init()
264 	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);  in axs101_early_init()
271 	iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */  in axs101_early_init()
274 	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);  in axs101_early_init()
277 	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);  in axs101_early_init()
280 	iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);  in axs101_early_init()
283 	iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);  in axs101_early_init()
335 	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);  in axs103_early_init()
337 	iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),  in axs103_early_init()
341 	iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX  in axs103_early_init()
345 	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);  in axs103_early_init()