Lines Matching +full:clock +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <33333333>;
68 reg_5v0: regulator-5v0 {
69 compatible = "regulator-fixed";
71 regulator-name = "5v0-supply";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
76 cpu_intc: cpu-interrupt-controller {
77 compatible = "snps,archs-intc";
78 interrupt-controller;
79 #interrupt-cells = <1>;
82 idu_intc: idu-interrupt-controller {
83 compatible = "snps,archs-idu-intc";
84 interrupt-controller;
85 #interrupt-cells = <1>;
86 interrupt-parent = <&cpu_intc>;
90 compatible = "snps,archs-pct";
95 compatible = "snps,arc-timer";
97 interrupt-parent = <&cpu_intc>;
101 /* 64-bit Global Free Running Counter */
103 compatible = "snps,archs-timer-gfrc";
108 compatible = "simple-bus";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 interrupt-parent = <&idu_intc>;
115 cgu_rst: reset-controller@8a0 {
116 compatible = "snps,hsdk-reset";
117 #reset-cells = <1>;
121 core_clk: core-clk@0 {
122 compatible = "snps,hsdk-core-pll-clock";
124 #clock-cells = <0>;
128 * Set initial core pll output frequency to 1GHz.
132 assigned-clocks = <&core_clk>;
133 assigned-clock-rates = <1000000000>;
137 compatible = "snps,dw-apb-uart";
139 clock-frequency = <33330000>;
142 reg-shift = <2>;
143 reg-io-width = <4>;
147 compatible = "fixed-clock";
148 clock-frequency = <400000000>;
149 #clock-cells = <0>;
152 mmcclk_ciu: mmcclk-ciu {
153 compatible = "fixed-clock";
155 * DW sdio controller has external ciu clock divider
158 * but it divides by 8) SDIO IP uses wrong clock and
161 * divisor (div-by-2) in HSDK platform code.
162 * So add temporary fix and change clock frequency
165 clock-frequency = <50000000>;
166 #clock-cells = <0>;
169 mmcclk_biu: mmcclk-biu {
170 compatible = "fixed-clock";
171 clock-frequency = <400000000>;
172 #clock-cells = <0>;
175 gpu_core_clk: gpu-core-clk {
176 compatible = "fixed-clock";
177 clock-frequency = <400000000>;
178 #clock-cells = <0>;
181 gpu_dma_clk: gpu-dma-clk {
182 compatible = "fixed-clock";
183 clock-frequency = <400000000>;
184 #clock-cells = <0>;
187 gpu_cfg_clk: gpu-cfg-clk {
188 compatible = "fixed-clock";
189 clock-frequency = <200000000>;
190 #clock-cells = <0>;
193 dmac_core_clk: dmac-core-clk {
194 compatible = "fixed-clock";
195 clock-frequency = <400000000>;
196 #clock-cells = <0>;
199 dmac_cfg_clk: dmac-gpu-cfg-clk {
200 compatible = "fixed-clock";
201 clock-frequency = <200000000>;
202 #clock-cells = <0>;
206 #interrupt-cells = <1>;
210 interrupt-names = "macirq";
211 phy-mode = "rgmii";
213 snps,multicast-filter-bins = <256>;
215 clock-names = "stmmaceth";
216 phy-handle = <&phy0>;
218 reset-names = "stmmaceth";
219 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
220 dma-coherent;
222 tx-fifo-depth = <4096>;
223 rx-fifo-depth = <4096>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228 compatible = "snps,dwmac-mdio";
229 phy0: ethernet-phy@0 {
236 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
240 dma-coherent;
244 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
248 dma-coherent;
252 compatible = "altr,socfpga-dw-mshc";
254 num-slots = <1>;
255 fifo-depth = <16>;
256 card-detect-delay = <200>;
258 clock-names = "biu", "ciu";
260 bus-width = <4>;
261 dma-coherent;
265 compatible = "snps,dw-apb-ssi";
267 #address-cells = <1>;
268 #size-cells = <0>;
270 num-cs = <2>;
271 reg-io-width = <4>;
273 cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
276 spi-flash@0 {
277 compatible = "sst26wf016b", "jedec,spi-nor";
279 #address-cells = <1>;
280 #size-cells = <1>;
281 spi-max-frequency = <4000000>;
287 vref-supply = <®_5v0>;
288 spi-max-frequency = <1000000>;
293 compatible = "snps,creg-gpio-hsdk";
295 gpio-controller;
296 #gpio-cells = <2>;
301 compatible = "snps,dw-apb-gpio";
303 #address-cells = <1>;
304 #size-cells = <0>;
306 gpio_port_a: gpio-controller@0 {
307 compatible = "snps,dw-apb-gpio-port";
308 gpio-controller;
309 #gpio-cells = <2>;
310 snps,nr-gpios = <24>;
322 clock-names = "bus", "reg", "core", "shader";
327 compatible = "snps,axi-dma-1.01a";
331 clock-names = "core-clk", "cfgr-clk";
333 dma-channels = <4>;
334 snps,dma-masters = <2>;
335 snps,data-width = <3>;
336 snps,block-size = <4096 4096 4096 4096>;
338 snps,axi-max-burst-len = <16>;
343 #address-cells = <2>;
344 #size-cells = <2>;