Lines Matching refs:bandwidth
41 bandwidth in MBps
121 Memory bandwidth(MB) subdirectory contains the following files
125 The minimum memory bandwidth percentage which
129 The granularity in which the memory bandwidth
133 available bandwidth control steps are:
352 Memory bandwidth Allocation and monitoring
355 For Memory bandwidth resource, by default the user controls the resource
356 by indicating the percentage of total memory bandwidth.
358 The minimum bandwidth percentage value for each cpu model is predefined
359 and can be looked up through "info/MB/min_bandwidth". The bandwidth
361 be looked up at "info/MB/bandwidth_gran". The available bandwidth
365 The bandwidth throttling is a core specific mechanism on some of Intel
366 SKUs. Using a high bandwidth and a low bandwidth setting on two threads
368 low bandwidth. The fact that Memory bandwidth allocation(MBA) is a core
369 specific mechanism where as memory bandwidth monitoring(MBM) is done at
371 via the MBA and then monitor the bandwidth to see if the controls are
374 1. User may *not* see increase in actual bandwidth when percentage
377 This can occur when aggregate L2 external bandwidth is more than L3
378 external bandwidth. Consider an SKL SKU with 24 cores on a package and
379 where L2 external is 10GBps (hence aggregate L2 external bandwidth is
380 240GBps) and L3 external bandwidth is 100GBps. Now a workload with '20
381 threads, having 50% bandwidth, each consuming 5GBps' consumes the max L3
382 bandwidth of 100GBps although the percentage value specified is only 50%
383 << 100%. Hence increasing the bandwidth percentage will not yield any
384 more bandwidth. This is because although the L2 external bandwidth still
385 has capacity, the L3 external bandwidth is fully used. Also note that
388 2. Same bandwidth percentage may mean different actual bandwidth
391 For the same SKU in #1, a 'single thread, with 10% bandwidth' and '4
392 thread, with 10% bandwidth' can consume upto 10GBps and 40GBps although
393 they have same percentage bandwidth of 10%. This is simply because as
394 threads start using more cores in an rdtgroup, the actual bandwidth may
395 increase or vary although user specified bandwidth percentage is same.
398 resctrl added support for specifying the bandwidth in MBps as well. The
400 Controller(mba_sc)" which reads the actual bandwidth using MBM counters
401 and adjust the memory bandwidth percentages to ensure::
403 "actual bandwidth < user specified bandwidth".
405 By default, the schemata would take the bandwidth percentage values
437 Memory bandwidth Allocation (default mode)
445 Memory bandwidth Allocation specified in MBps
448 Memory bandwidth domain is L3 cache.
655 for cache bit masks, minimum b/w of 10% with a memory bandwidth
760 50% of the L3 cache on socket 0, and 50% of memory bandwidth on socket 0
766 to the "top" 50% of the cache on socket 0 and 50% of memory bandwidth on
775 also get 50% of memory bandwidth assuming that the cores 4-7 are SMT