Lines Matching full:instruction
22 "Sources" generate a compressed stream representing the processor instruction
274 comparator with "_stext" and "_etext", essentially tracing any instruction
314 Instruction 106378866 0x8026B53C E52DE004 false PUSH {lr}
315 Instruction 0 0x8026B540 E24DD00C false SUB sp,sp,#0xc
316 Instruction 0 0x8026B544 E3A03000 false MOV r3,#0
317 Instruction 0 0x8026B548 E58D3004 false STR r3,[sp,#4]
318 Instruction 0 0x8026B54C E59D3004 false LDR r3,[sp,#4]
319 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
320 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
321 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
322 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
324 Instruction 319 0x8026B54C E59D3004 false LDR r3,[sp,#4]
325 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
326 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
327 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
328 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
329 Instruction 9 0x8026B54C E59D3004 false LDR r3,[sp,#4]
330 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
331 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
332 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
333 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
334 Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4]
335 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
336 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
337 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
338 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
339 Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4]
340 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
341 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
342 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
343 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
344 Instruction 10 0x8026B54C E59D3004 false LDR r3,[sp,#4]
345 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
346 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
347 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
348 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
349 Instruction 6 0x8026B560 EE1D3F30 false MRC p15,#0x0,r3,c13,c0,#1
350 Instruction 0 0x8026B564 E1A0100D false MOV r1,sp
351 Instruction 0 0x8026B568 E3C12D7F false BIC r2,r1,#0x1fc0
352 Instruction 0 0x8026B56C E3C2203F false BIC r2,r2,#0x3f
353 Instruction 0 0x8026B570 E59D1004 false LDR r1,[sp,#4]
354 …Instruction 0 0x8026B574 E59F0010 false LDR r0,[pc,#16] ; [0x8026B58C…
355 Instruction 0 0x8026B578 E592200C false LDR r2,[r2,#0xc]
356 Instruction 0 0x8026B57C E59221D0 false LDR r2,[r2,#0x1d0]
357 …Instruction 0 0x8026B580 EB07A4CF true BL {pc}+0x1e9344 ; 0x804548c4
359 Instruction 13570831 0x8026B584 E28DD00C false ADD sp,sp,#0xc
360 Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc}
422 synthesizing instruction and branch events from the instruction trace.
428 required to support instruction decode of 32-bit Arm programs.