Lines Matching refs:RELEASE

479      An ACQUIRE operation should almost always be paired with a RELEASE
483  (6) RELEASE operations.
486      memory operations before the RELEASE operation will appear to happen
487      before the RELEASE operation with respect to the other components of the
488      system. RELEASE operations include UNLOCK operations and
491      Memory operations that occur after a RELEASE operation may appear to
494      The use of ACQUIRE and RELEASE operations generally precludes the need
496      the subsection "MMIO write barrier").  In addition, a RELEASE+ACQUIRE
499      RELEASE on that same variable are guaranteed to be visible.  In other
505      RELEASE acts as a minimal "release" operation.
508 RELEASE variants in addition to fully-ordered and relaxed (no barrier
510 store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
1963 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
1974  (2) RELEASE operation implication:
1976      Memory operations issued before the RELEASE will be completed before the
1977      RELEASE operation has completed.
1979      Memory operations issued after the RELEASE may be completed before the
1980      RELEASE operation has completed.
1987  (4) ACQUIRE vs RELEASE implication:
1989      All ACQUIRE operations issued before a RELEASE operation will be
1990      completed before the RELEASE operation.
2003 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
2005 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
2010 	RELEASE M
2015 	ACQUIRE M, STORE *B, STORE *A, RELEASE M
2017 When the ACQUIRE and RELEASE are a lock acquisition and release,
2019 RELEASE are to the same lock variable, but only from the perspective of
2021 RELEASE may -not- be assumed to be a full memory barrier.
2023 Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
2025 critical sections corresponding to the RELEASE and the ACQUIRE can cross,
2029 	RELEASE M
2035 	ACQUIRE N, STORE *B, STORE *A, RELEASE M
2039 the RELEASE would simply complete, thereby avoiding the deadlock.
2079 	RELEASE
2085 	ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
2091 	{*F,*A}, *B,	ACQUIRE, *C, *D,	RELEASE, *E
2092 	*A, *B, *C,	ACQUIRE, *D,		RELEASE, *E, *F
2093 	*A, *B,		ACQUIRE, *C,		RELEASE, *D, *E, *F
2094 	*B,		ACQUIRE, *C, *D,	RELEASE, {*F,*A}, *E
2102 (RELEASE equivalent) will act as compiler barriers only.  So if memory or I/O
2288 	RELEASE M			RELEASE Q
2295 	*E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2300 	*A, *B or *C following RELEASE M
2302 	*E, *F or *G following RELEASE Q
2368 	RELEASE task
2410 	RELEASE task