Lines Matching refs:CPU
65 - CPU memory barriers.
75 (*) Inter-CPU acquiring barrier effects.
121 | CPU 1 |<----->| Memory |<----->| CPU 2 |
138 Each CPU executes a program that generates memory access operations. In the
139 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
146 CPU are perceived by the rest of the system as the operations cross the
147 interface between the CPU and rest of the system (the dotted lines).
152 CPU 1 CPU 2
179 Furthermore, the stores committed by a CPU to the memory system may not be
180 perceived by the loads made by another CPU in the same order as the stores were
186 CPU 1 CPU 2
193 the address retrieved from P by CPU 2. At the end of the sequence, any of the
200 Note that CPU 2 will never try and load C into D because the CPU will load P
229 There are some minimal guarantees that may be expected of a CPU:
231 (*) On any given CPU, dependent memory accesses will be issued in order, with
236 the CPU will issue the following memory operations:
241 emits a memory-barrier instruction, so that a DEC Alpha CPU will
249 (*) Overlapping loads and stores within a particular CPU will appear to be
250 ordered within that CPU. This means that for:
254 the CPU will only issue the following sequence of memory operations:
262 the CPU will only issue:
362 in random order, but this can be a problem for CPU-CPU interaction and for I/O.
364 CPU to restrict the order.
392 A CPU can be viewed as committing a sequence of store operations to the
414 committing sequences of stores to the memory system that the CPU being
415 considered can then perceive. A data dependency barrier issued by the CPU
417 load touches one of a sequence of stores from another CPU, then by the
514 between two CPUs or between a CPU and a device. If it can be guaranteed that
531 instruction; the barrier can be considered to draw a line in that CPU's
534 (*) There is no guarantee that issuing a memory barrier on one CPU will have
535 any direct effect on another CPU or any other hardware in the system. The
536 indirect effect will be the order in which the second CPU sees the effects
537 of the first CPU's accesses occur, but see the next point:
539 (*) There is no guarantee that a CPU will see the correct order of effects
540 from a second CPU's accesses, even _if_ the second CPU uses a memory
541 barrier, unless the first CPU _also_ uses a matching memory barrier (see
544 (*) There is no guarantee that some intervening piece of off-the-CPU
545 hardware[*] will not reorder the memory accesses. CPU cache coherency
570 CPU 1 CPU 2
585 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
597 CPU 1 CPU 2
616 even-numbered bank of the reading CPU's cache is extremely busy while the
629 CPU 1 CPU 2
652 the CPU containing it. See the section on "Multicopy atomicity" for
683 dependency, but rather a control dependency that the CPU may short-circuit
715 b = 1; /* BUG: Compiler and CPU can both reorder!!! */
748 'b', which means that the CPU is within its rights to reorder them:
799 Given this transformation, the CPU is not required to respect the ordering
865 A weakly ordered CPU would have no dependency of any sort between the load
874 to the CPU containing it. See the section on "Multicopy atomicity"
926 When dealing with CPU-CPU interactions, certain types of memory barrier should
939 CPU 1 CPU 2
949 CPU 1 CPU 2
959 CPU 1 CPU 2
977 CPU 1 CPU 2
992 CPU 1
1012 | CPU 1 | : | B=2 | }
1023 | memory system by CPU 1
1030 CPU 1 CPU 2
1040 Without intervention, CPU 2 may perceive the events on CPU 1 in some
1041 effectively random order, despite the write barrier issued by CPU 1:
1046 | | : +------+ \ +-------+ | CPU 2
1047 | CPU 1 | : | A=1 | \ --->| C->&Y | V
1057 | : : | CPU 2 |
1070 In the above example, CPU 2 perceives that B is 7, despite the load of *C
1074 and the load of *C (ie: B) on CPU 2:
1076 CPU 1 CPU 2
1093 | CPU 1 | : | A=1 | \ --->| C->&Y |
1103 | : : | CPU 2 |
1117 CPU 1 CPU 2
1126 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1127 some effectively random order, despite the write barrier issued by CPU 1:
1133 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1139 | +-------+ | CPU 2 |
1151 load of A on CPU 2:
1153 CPU 1 CPU 2
1163 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1170 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1176 | +-------+ | CPU 2 |
1182 to be perceptible to CPU 2 +-------+ | |
1189 CPU 1 CPU 2
1207 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1213 | +-------+ | CPU 2 |
1222 to be perceptible to CPU 2 +-------+ | |
1226 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1233 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1239 | +-------+ | CPU 2 |
1264 actual load instruction to potentially complete immediately because the CPU
1267 It may turn out that the CPU didn't actually need the value - perhaps because a
1273 CPU 1 CPU 2
1285 +-------+ | CPU 2 |
1288 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1294 the CPU can then perform the : : | |
1301 CPU 1 CPU 2
1316 +-------+ | CPU 2 |
1319 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1332 but if there was an update or an invalidation from another CPU pending, then
1338 +-------+ | CPU 2 |
1341 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1369 CPU 1 CPU 2 CPU 3
1376 Suppose that CPU 2's load from X returns 1, which it then stores to Y,
1377 and CPU 3's load from Y returns 1. This indicates that CPU 1's store
1378 to X precedes CPU 2's load from X and that CPU 2's store to Y precedes
1379 CPU 3's load from Y. In addition, the memory barriers guarantee that
1380 CPU 2 executes its load before its store, and CPU 3 loads from Y before
1381 it loads from X. The question is then "Can CPU 3's load from X return 0?"
1383 Because CPU 3's load from X in some sense comes after CPU 2's load, it
1384 is natural to expect that CPU 3's load from X must therefore return 1.
1386 on CPU B follows a load from the same variable executing on CPU A (and
1387 CPU A did not originally store the value which it read), then on
1388 multicopy-atomic systems, CPU B's load must return either the same value
1389 that CPU A's load did or some later value. However, the Linux kernel
1393 for any lack of multicopy atomicity. In the example, if CPU 2's load
1394 from X returns 1 and CPU 3's load from Y returns 1, then CPU 3's load
1399 that CPU 2's general barrier is removed from the above example, leaving
1402 CPU 1 CPU 2 CPU 3
1410 this example, it is perfectly legal for CPU 2's load from X to return 1,
1411 CPU 3's load from Y to return 1, and its load from X to return 0.
1413 The key point is that although CPU 2's data dependency orders its load
1414 and store, it does not guarantee to order CPU 1's store. Thus, if this
1416 store buffer or a level of cache, CPU 2 might have early access to CPU 1's
1513 (*) CPU memory barriers.
1547 to the same variable, and in some cases, the CPU is within its
1555 Prevent both the compiler and the CPU from doing this as follows:
1599 a was modified by some other CPU between the "while" statement and
1626 will carry out its proof assuming that the current CPU is the only
1648 Again, the compiler assumes that the current CPU is the only one
1659 surprise if some other CPU might have stored to variable 'a' in the
1732 though the CPU of course need not do so.
1750 could cause some other CPU to see a spurious value of 42 -- even
1817 Please note that these compiler barriers have no direct effect on the CPU,
1821 CPU MEMORY BARRIERS
1824 The Linux kernel has eight basic CPU memory barriers:
1848 systems because it is assumed that a CPU will appear to be self-consistent,
1861 compiler and the CPU from reordering them.
1900 of writes or reads of shared memory accessible to both the CPU and a
1905 to the device or the CPU, and a doorbell to notify it when new
2020 another CPU not holding that lock. In short, a ACQUIRE followed by an
2024 not imply a full memory barrier. Therefore, the CPU's execution of the
2043 One key point is that we are only talking about the CPU doing
2048 But suppose the CPU reordered the operations. In this case,
2049 the unlock precedes the lock in the assembly code. The CPU
2052 try to sleep, but more on that later). The CPU will eventually
2069 See also the section on "Inter-CPU acquiring barrier effects".
2129 CPU 1
2172 CPU 1 (Sleeper) CPU 2 (Waker)
2181 where "task" is the thread being woken up and it equals CPU 1's "current".
2188 CPU 1 CPU 2
2268 INTER-CPU ACQUIRING BARRIER EFFECTS
2282 CPU 1 CPU 2
2291 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2326 When there's a system with more than one processor, more than one CPU in the
2377 another CPU might start processing the waiter and might clobber the waiter's
2382 CPU 1 CPU 2
2420 right order without actually intervening in the CPU. Since there's only one
2421 CPU, that CPU's dependency ordering logic will take care of everything else.
2438 Many devices can be memory mapped, and so appear to the CPU as if they're just
2442 However, having a clever CPU or a clever compiler creates a potential problem
2444 device in the requisite order if the CPU or the compiler thinks it is more
2468 routine is executing, the driver's core may not run on the same CPU, and its
2527 by the same CPU thread to a particular device will arrive in program
2530 2. A writeX() issued by a CPU thread holding a spinlock is ordered
2531 before a writeX() to the same peripheral from another CPU thread
2537 3. A writeX() by a CPU thread to the peripheral will first wait for the
2539 propagated to, the same thread. This ensures that writes by the CPU
2541 visible to a DMA engine when the CPU writes to its MMIO control
2544 4. A readX() by a CPU thread from the peripheral will complete before
2546 ensures that reads by the CPU from an incoming DMA buffer allocated
2551 5. A readX() by a CPU thread from the peripheral will complete before
2553 This ensures that two MMIO register writes by the CPU to a peripheral
2574 respect to other accesses from the same CPU thread to the same
2592 Since many CPU architectures ultimately access these peripherals via an
2624 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2630 This means that it must be considered that the CPU will execute its instruction
2641 A CPU may also discard any instruction sequence that winds up having no
2652 THE EFFECTS OF THE CPU CACHE
2659 As far as the way a CPU interacts with another part of the system through the
2660 caches goes, the memory system has to include the CPU's caches, and memory
2661 barriers for the most part act at the interface between the CPU and its cache
2664 <--- CPU ---> : <----------- Memory ----------->
2668 | CPU | | Memory | : | CPU | | | | |
2678 | CPU | | Memory | : | CPU | | |--->| Device |
2687 CPU that issued it since it may have been satisfied within the CPU's own cache,
2690 cacheline over to the accessing CPU and propagate the effects upon conflict.
2692 The CPU core may execute instructions in any order it deems fit, provided the
2700 accesses cross from the CPU side of things to the memory side of things, and
2704 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2709 the use of any special device communication instructions the CPU may have.
2717 will be ordered. This means that while changes made on one CPU will
2723 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2730 | CPU 1 |<---+ | |
2738 | CPU 2 |<---+ | |
2753 (*) while the CPU core is interrogating one cache, the other cache may be
2764 Imagine, then, that two writes are made on the first CPU, with a write barrier
2765 between them to guarantee that they will appear to reach that CPU's caches in
2768 CPU 1 CPU 2 COMMENT
2779 the local CPU's caches have apparently been updated in the correct order. But
2780 now imagine that the second CPU wants to read those values:
2782 CPU 1 CPU 2 COMMENT
2789 cacheline holding p may get updated in one of the second CPU's caches while
2791 CPU's caches by some other cache event:
2793 CPU 1 CPU 2 COMMENT
2809 Basically, while both cachelines will be updated on CPU 2 eventually, there's
2811 as that committed on CPU 1.
2819 CPU 1 CPU 2 COMMENT
2845 permitted Alpha to sport higher CPU clock rates back in the day. However,
2857 the kernel must flush the overlapping bits of cache on each CPU (and maybe
2861 cache lines being written back to RAM from a CPU's cache after the device has
2862 installed its own data, or cache lines present in the CPU's cache may simply
2864 is discarded from the CPU's cache and reloaded. To deal with this, the
2866 cache on each CPU.
2875 a window in the CPU's memory space that has different properties assigned than
2890 A programmer might take it for granted that the CPU will perform memory
2891 operations in exactly the order specified, so that if the CPU is, for example,
2900 they would then expect that the CPU will complete the memory operation for each
2921 of the CPU buses and caches;
2928 (*) the CPU's data cache may affect the ordering, and while cache-coherency
2933 So what another CPU, say, might actually observe from the above piece of code
2941 However, it is guaranteed that a CPU will be self-consistent: it will see its
2960 The code above may cause the CPU to generate the full sequence of memory
2969 where a given CPU might reorder successive loads to the same location.
2976 the CPU even sees them.
2999 and the LOAD operation never appear outside of the CPU.
3005 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
3006 some versions of the Alpha CPU have a split data cache, permitting them to have