Lines Matching refs:IPC
34 | EHCI/XHCI | --> | ISH IPC |
90 | IPC Drivers |
110 3.2 Inter Processor Communication (IPC) driver
115 The IPC message used memory mapped I/O. The registers are defined in
118 3.2.1 IPC/FW message types
128 RX (E.g.IPC_REG_ISH2HOST_MSG, IPC_REG_HOST2ISH_MSG). The IPC layer maintains
140 Bits 16..19: management command (for IPC management protocol)
147 To abstract HW level IPC communication, a set of callbacks are registered.
192 whether to send over IPC or over DMA; for each transfer the decision is
215 (up to IPC MTU), thus allowing for interrupt throttling.
216 Currently, ISH FW decides to send over DMA if ISHTP message is more than 3 IPC
217 fragments and via IPC otherwise.
280 HID-ISH-CLN ISHTP IPC HW