Lines Matching refs:Feature

2 FPGA Device Feature List (DFL) Framework Overview
11 The Device Feature List (DFL) FPGA framework (and drivers according to this
19 Device Feature List (DFL) Overview
21 Device Feature List (DFL) defines a linked list of feature headers within the
31  +----------+  |   | Feature  |  |   | Feature  |  |   | Feature  |
37  +----------+  |   | Feature  |      | Feature  |      | Feature  |
65 Feature Header (Next_DFH) pointer.
67 Each FIU, AFU and Private Feature could implement its own functional registers.
69 e.g. FME Header Register Set, and the one for Private Feature, is named as
70 Feature Register Set, e.g. FME Partial Reconfiguration Feature Register Set.
72 This Device Feature List provides a way of linking features together, it's
167                  | FPGA Container Device |    Device Feature List
181 given Device Feature Lists and create platform devices for feature devices
238 Feature Lists, as illustrated below:
388 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)