Lines Matching refs:FPGA
2 FPGA Device Feature List (DFL) Framework Overview
11 The Device Feature List (DFL) FPGA framework (and drivers according to this
14 configure, enumerate, open and access FPGA accelerators on platforms which
16 enables system level management functions such as FPGA reconfiguration.
23 walk through these predefined data structures to enumerate FPGA features:
24 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
55 FPGA Interface Unit (FIU) represents a standalone functional unit for the
56 interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more
59 Accelerated Function Unit (AFU) represents a FPGA programmable region and
74 and can be implemented in register regions of any FPGA device.
77 FIU - FME (FPGA Management Engine)
79 The FPGA Management Engine performs reconfiguration and other infrastructure
80 functions. Each FPGA device only has one FME.
97 bitstream_id indicates version of the static FPGA region.
100 bitstream_metadata includes detailed information of static FPGA region,
104 one FPGA device may have more than one port, this sysfs interface indicates
105 how many ports the FPGA device has.
114 A port represents the interface between the static FPGA fabric and a partially
116 to the accelerator and exposes features such as reset and debug. Each FPGA
139 reset the FPGA Port and its AFU. Userspace can do Port
167 | FPGA Container Device | Device Feature List
168 | (FPGA Base Region) | Framework
172 | FPGA DFL Device Module |
176 | FPGA Hardware Device |
180 (FPGA base region), discover feature devices and their private features from the
186 The FPGA DFL Device could be different hardwares, e.g. PCIe device, platform
193 The FPGA Management Engine (FME) driver is a platform driver which is loaded
195 provides the key features for FPGA management, including:
197 a) Expose static FPGA region information, e.g. version and metadata.
201 b) Partial Reconfiguration. The FME driver creates FPGA manager, FPGA
202 bridges and FPGA regions during PR sub feature initialization. Once
204 common interface function from FPGA Region to complete the partial
207 Similar to the FME driver, the FPGA Accelerated Function Unit (AFU) driver is
223 generated for the exact static FPGA region and targeted reconfigurable region
224 (port) of the FPGA, otherwise, the reconfiguration operation will fail and
227 the compat_id exposed by the target FPGA region. This check is usually done by
231 FPGA virtualization - PCIe SRIOV
233 This section describes the virtualization support on DFL based FPGA device to
235 (VM). This section only describes the PCIe based FPGA device with SRIOV support.
237 Features supported by the particular FPGA device are exposed through Device
258 | DFL based FPGA PCIe Device |
273 | FPGA || FPGA || FPGA | |
281 | FPGA Container Device | | | FPGA Container Device |
282 | (FPGA Base Region) | | | (FPGA Base Region) |
285 | FPGA PCIE Module | | Virtual | FPGA PCIE Module |
292 FPGA PCIe device driver is always loaded first once a FPGA PCIe PF or VF device
295 * Finishes enumeration on both FPGA PCIe PF and VF device using common
331 In the example below, two DFL based FPGA devices are installed in the host. Each
334 FPGA regions are created under /sys/class/fpga_region/::
343 fpga region which represents the FPGA device.