Lines Matching full:transfer

21 will want to start a transfer, it will assert a DMA request (DRQ) by
25 parameter: the transfer size. At each clock cycle, it would transfer a
26 byte of data from one buffer to another, until the transfer size has
31 cycle. For example, we may want to transfer as much data as the
36 parameter called the transfer width.
44 transfer into smaller sub-transfers.
59 transfer, and whenever the transfer is started, the controller will go
73 transfer width and the transfer size.
118   should contain a bitmask of the supported source transfer width
121   should contain a bitmask of the supported destination transfer width
128   granularity of the transfer residue reported to dma_set_residue.
188   - The device is able to trigger a dummy transfer that will
216   - If you want to transfer a single contiguous memory buffer,
223   - A cyclic transfer is a transfer where the chunk collection will
231   - The device supports interleaved transfer.
233   - These transfers can transfer data from a non-contiguous buffer
235     transfer data from a non-contiguous data set to a continuous
239     want to transfer a portion of uncompressed data directly to the
246 after each transfer. In case of a ring buffer, they may loop
280     for the transfer being prepared, and should create a hardware
290     during the transfer setup at probe time to avoid putting to
295     particular transfer.
318     - result: This provides the transfer result defined by
321     - residue: Provides the residue bytes of the transfer for those that
327     and starts the transfer. Whenever that transfer is done, it
343   - In the case of a cyclic transfer, it should only take into
370   - Pauses a transfer on the channel
377   - Resumes a transfer on the channel
393     wait until the currently active transfer has completely stopped.
419 - Should be called at the end of an async TX transfer, and can be
455   because the DMA'd data wasn't used, it can resubmit the transfer right after
482 that handles the end of transfer interrupts in the handler, but defer
483 most work to a tasklet, including the start of a new transfer whenever
484 the previous transfer ended.
486 This is a rather inefficient design though, because the inter-transfer
489 in between, which will slow down the global transfer rate.
492 transfer in your tasklet, move that part to the interrupt handler in
504 - Transfer: A collection of chunks (be it contiguous or not)