Lines Matching +full:non +full:- +full:armv7

1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Marc Zyngier <marc.zyngier@arm.com>
11   - Mark Rutland <mark.rutland@arm.com>
13   ARM cores may have a per-core architected timer, which provides per-cpu timers,
17   The per-core architected timer is attached to a GIC to deliver its
18   per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24       - items:
25           - enum:
26               - arm,cortex-a15-timer
27           - enum:
28               - arm,armv7-timer
29       - items:
30           - enum:
31             - arm,armv7-timer
32       - items:
33           - enum:
34             - arm,armv8-timer
38       - description: secure timer irq
39       - description: non-secure timer irq
40       - description: virtual timer irq
41       - description: hypervisor timer irq
43   clock-frequency:
49   always-on:
51     description: If present, the timer is powered through an always-on power
54   fsl,erratum-a008585:
56     description: Indicates the presence of QorIQ erratum A-008585, which says
58       by back-to-back reads. This also affects writes to the tval register, due
61   hisilicon,erratum-161010101:
68   arm,cpu-registers-not-fw-configured:
71       registers, which contain their architecturally-defined reset values. Only
72       supported for 32-bit systems which follow the ARMv7 architected reset
75   arm,no-tick-in-suspend:
78       low-power system suspend on some SoCs. This behavior does not match the
80       be implemented in an always-on power domain."
83   - compatible
86   - required:
87       - interrupts
88   - required:
89       - interrupts-extended
92   - |
94       compatible = "arm,cortex-a15-timer",
95              "arm,armv7-timer";
100       clock-frequency = <100000000>;