Lines Matching +full:spi +full:- +full:tx +full:- +full:delay +full:- +full:us
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Generic Binding
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-[0-9a-f])*$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
35 cs-gpios looks like this
36 cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
45 num-cs:
50 spi-slave:
53 The SPI controller acts as a slave, instead of a master.
62 Compatible of the SPI device.
65 - compatible
67 "^.*@[0-9a-f]+$":
73 Compatible of the SPI device.
81 spi-3wire:
84 The device requires 3-wire mode.
86 spi-cpha:
91 spi-cpol:
96 spi-cs-high:
101 spi-lsb-first:
106 spi-max-frequency:
109 Maximum SPI clocking speed of the device in Hz.
111 spi-rx-bus-width:
113 - $ref: /schemas/types.yaml#/definitions/uint32
114 - enum: [ 1, 2, 4 ]
115 - default: 1
117 Bus width to the SPI bus used for MISO.
119 spi-rx-delay-us:
121 Delay, in microseconds, after a read transfer.
123 spi-tx-bus-width:
125 - $ref: /schemas/types.yaml#/definitions/uint32
126 - enum: [ 1, 2, 4 ]
127 - default: 1
129 Bus width to the SPI bus used for MOSI.
131 spi-tx-delay-us:
133 Delay, in microseconds, after a write transfer.
136 - compatible
137 - reg
140 - |
141 spi@f00 {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
147 interrupt-parent = <&mpc5200_pic>;
149 ethernet-switch@0 {
151 spi-max-frequency = <1000000>;
157 spi-max-frequency = <100000>;