Lines Matching +full:reset +full:- +full:names
8 - compatible: compatible list, contains:
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
13 "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
14 "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
15 "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
16 "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
17 "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
19 - reg:
20 - index 0: address and length of register set for PHY's common
22 - index 1: address and length of the DP_COM control block (for
23 "qcom,sdm845-qmp-usb3-phy" only).
25 - reg-names:
26 - For "qcom,sdm845-qmp-usb3-phy":
27 - Should be: "reg-base", "dp_com"
28 - For all others:
29 - The reg-names property shouldn't be defined.
31 - #address-cells: must be 1
32 - #size-cells: must be 1
33 - ranges: must be present
35 - clocks: a list of phandles and clock-specifier pairs,
36 one for each entry in clock-names.
37 - clock-names: "cfg_ahb" for phy config clock,
43 For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
44 For "qcom,msm8996-qmp-pcie-phy" must contain:
46 For "qcom,msm8996-qmp-usb3-phy" must contain:
48 For "qcom,msm8998-qmp-usb3-phy" must contain:
50 For "qcom,msm8998-qmp-ufs-phy" must contain:
52 For "qcom,msm8998-qmp-pcie-phy" must contain:
54 For "qcom,sdm845-qmp-usb3-phy" must contain:
56 For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
58 For "qcom,sdm845-qmp-ufs-phy" must contain:
61 - resets: a list of phandles and reset controller specifier pairs,
62 one for each entry in reset-names.
63 - reset-names: "phy" for reset of phy block,
64 "common" for phy common block reset,
65 "cfg" for phy's ahb cfg block reset,
66 "ufsphy" for the PHY reset in the UFS controller.
68 For "qcom,ipq8074-qmp-pcie-phy" must contain:
70 For "qcom,msm8996-qmp-pcie-phy" must contain:
72 For "qcom,msm8996-qmp-usb3-phy" must contain
74 For "qcom,msm8998-qmp-usb3-phy" must contain
76 For "qcom,msm8998-qmp-ufs-phy": must contain:
78 For "qcom,msm8998-qmp-pcie-phy" must contain:
80 For "qcom,sdm845-qmp-usb3-phy" must contain:
82 For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
84 For "qcom,sdm845-qmp-ufs-phy": must contain:
87 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
88 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
91 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
95 - Each device node of QMP phy is required to have as many child nodes as
99 - reg: list of offset and length pairs of register sets for PHY blocks -
101 - #phy-cells: must be 0
103 Required properties for a single "lanes" child node of non-PCIe PHYs:
104 - reg: list of offset and length pairs of register sets for PHY blocks
105 For 1-lane devices:
107 For 2-lane devices:
109 - #phy-cells: must be 0
112 - clocks: a list of phandles and clock-specifier pairs,
113 one for each entry in clock-names.
114 - clock-names: Must contain following:
115 "pipe<lane-number>" for pipe clock specific to each lane.
116 - clock-output-names: Name of the PHY clock that will be the parent for
118 For "qcom,ipq8074-qmp-pcie-phy":
119 - "pcie20_phy0_pipe_clk" Pipe Clock parent
122 - #clock-cells: must be 0
123 - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
124 gate-controlled by the gcc.
126 Required properties for child node of PHYs with lane reset, AKA:
127 "qcom,msm8996-qmp-pcie-phy"
128 - resets: a list of phandles and reset controller specifier pairs,
129 one for each entry in reset-names.
130 - reset-names: Must contain following:
131 "lane<lane-number>" for reset specific to each lane.
135 compatible = "qcom,msm8996-qmp-pcie-phy";
137 #address-cells = <1>;
138 #size-cells = <1>;
144 clock-names = "aux", "cfg_ahb", "ref";
146 vdda-phy-supply = <&pm8994_l28>;
147 vdda-pll-supply = <&pm8994_l12>;
152 reset-names = "phy", "common", "cfg";
158 #clock-cells = <0>;
159 #phy-cells = <0>;
162 clock-names = "pipe0";
163 clock-output-names = "pcie_0_pipe_clk_src";
165 reset-names = "lane0";
174 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
176 #address-cells = <1>;
177 #size-cells = <1>;
184 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
188 reset-names = "phy", "common";
195 #clock-cells = <0>;
196 #phy-cells = <0>;
198 clock-names = "pipe0";
199 clock-output-names = "usb3_uni_phy_pipe_clk_src";
204 compatible = "qcom,sdm845-qmp-ufs-phy";
206 #address-cells = <1>;
207 #size-cells = <1>;
209 clock-names = "ref",
220 #phy-cells = <0>;