Lines Matching full:for
4 QMP phy controller supports physical layer functionality for a number of
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
13 "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
14 "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
15 "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
16 "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
17 "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
20 - index 0: address and length of register set for PHY's common
22 - index 1: address and length of the DP_COM control block (for
26 - For "qcom,sdm845-qmp-usb3-phy":
28 - For all others:
36 one for each entry in clock-names.
37 - clock-names: "cfg_ahb" for phy config clock,
38 "aux" for phy aux clock,
39 "ref" for 19.2 MHz ref clk,
40 "com_aux" for phy common block aux clock,
41 "ref_aux" for phy reference aux clock,
43 For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
44 For "qcom,msm8996-qmp-pcie-phy" must contain:
46 For "qcom,msm8996-qmp-usb3-phy" must contain:
48 For "qcom,msm8998-qmp-usb3-phy" must contain:
50 For "qcom,msm8998-qmp-ufs-phy" must contain:
52 For "qcom,msm8998-qmp-pcie-phy" must contain:
54 For "qcom,sdm845-qmp-usb3-phy" must contain:
56 For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
58 For "qcom,sdm845-qmp-ufs-phy" must contain:
62 one for each entry in reset-names.
63 - reset-names: "phy" for reset of phy block,
64 "common" for phy common block reset,
65 "cfg" for phy's ahb cfg block reset,
66 "ufsphy" for the PHY reset in the UFS controller.
68 For "qcom,ipq8074-qmp-pcie-phy" must contain:
70 For "qcom,msm8996-qmp-pcie-phy" must contain:
72 For "qcom,msm8996-qmp-usb3-phy" must contain
74 For "qcom,msm8998-qmp-usb3-phy" must contain
76 For "qcom,msm8998-qmp-ufs-phy": must contain:
78 For "qcom,msm8998-qmp-pcie-phy" must contain:
80 For "qcom,sdm845-qmp-usb3-phy" must contain:
82 For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
84 For "qcom,sdm845-qmp-ufs-phy": must contain:
98 Required properties for child nodes of PCIe PHYs (one child per lane):
99 - reg: list of offset and length pairs of register sets for PHY blocks -
103 Required properties for a single "lanes" child node of non-PCIe PHYs:
104 - reg: list of offset and length pairs of register sets for PHY blocks
105 For 1-lane devices:
107 For 2-lane devices:
111 Required properties for child node of PCIe and USB3 qmp phys:
113 one for each entry in clock-names.
115 "pipe<lane-number>" for pipe clock specific to each lane.
116 - clock-output-names: Name of the PHY clock that will be the parent for
118 For "qcom,ipq8074-qmp-pcie-phy":
123 - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
126 Required properties for child node of PHYs with lane reset, AKA:
129 one for each entry in reset-names.
131 "lane<lane-number>" for reset specific to each lane.